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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Owyang; King
Address:
Atherton, CA
No. of patents:
24
Patents:












Patent Number Title Of Patent Date Issued
8269263 High current density power field effect transistor September 18, 2012
An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first
7595547 Semiconductor die package including cup-shaped leadframe September 29, 2009
A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side
7394150 Semiconductor package including die interposed between cup-shaped lead frame and lead frame havi July 1, 2008
A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of
7326995 Trench MIS device having implanted drain-drift region and thick bottom oxide February 5, 2008
A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating
7238551 Method of fabricating semiconductor package including die interposed between cup-shaped lead fra July 3, 2007
A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of
7033876 Trench MIS device having implanted drain-drift region and thick bottom oxide and process for man April 25, 2006
A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating
6909170 Semiconductor assembly with package using cup-shaped lead-frame June 21, 2005
A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side
6744124 Semiconductor die package including cup-shaped leadframe June 1, 2004
A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side
5910669 Field effect Trench transistor having lightly doped epitaxial region on the surface portion ther June 8, 1999
A DMOS field effect transistor having its gate electrode located in a trench includes a lightly doped epitaxial layer overlying the usual epitaxial layer. The trench penetrates only part way through the upper epitaxial layer which is more lightly doped than is the underlying lower ep
5767578 Surface mount and flip chip technology with diamond film passivation for total integated circuit June 16, 1998
An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat
5757081 Surface mount and flip chip technology for total integrated circuit isolation May 26, 1998
An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat
5753529 Surface mount and flip chip technology for total integrated circuit isolation May 19, 1998
An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat
5639676 Trenched DMOS transistor fabrication having thick termination region oxide June 17, 1997
A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The
5578851 Trenched DMOS transistor having thick field oxide in termination region November 26, 1996
A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The
5532179 Method of making a field effect trench transistor having lightly doped epitaxial region on the s July 2, 1996
A DMOS field effect transistor having its gate electrode located in a trench includes a lightly doped epitaxial layer overlying the usual epitaxial layer. The trench penetrates only part way through the upper epitaxial layer which is more lightly doped than is the underlying lower ep
5521409 Structure of power mosfets, including termination structures May 28, 1996
A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002), typically of substantially uniform thickness, lies over the active and termination areas. A main polycrystalline portion (2003
5517379 Reverse battery protection device containing power MOSFET May 14, 1996
A device for protecting battery-powered semiconductor devices and the like against a reverse battery condition. During normal operation a charge pump charges the gate of a power MOSFET, turning the MOSFET on and providing a low-resistance power supply path from the battery to the load. I
5468982 Trenched DMOS transistor with channel block at cell trench corners November 21, 1995
A trenched DMOS transistor has improved device performance and production yield. During fabrication the cell trench corners, i.e. the areas where two trenches intersect, are covered on the principal surface of the integrated circuit substrate with a blocking photoresist layer during the
5429964 Low on-resistance power MOS technology July 4, 1995
A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow
5426325 Metal crossover in high voltage IC with graduated doping control June 20, 1995
Non-uniformly doped regions are formed adjacent to semiconductor junctions which underlie high voltage crossovers. The non-uniformly doped regions prevent junction breakdown caused by strong electric fields. The voltage drop between a crossover and an element of an integrated circuit is
5404040 Structure and fabrication of power MOSFETs, including termination structures April 4, 1995
A power MOSFET is created from a semiconductor body (2000 and 2001) having a main active area and a peripheral termination area. A first insulating layer (2002) of substantially uniform thickness lies over the active and termination areas. A main polycrystalline portion (2003A/2003B) lie
5316959 Trenched DMOS transistor fabrication using six masks May 31, 1994
A trenched DMOS transistor is fabricated using six masking steps. One masking step defines both the P+ regions and the active portions of the transistor which are masked using a LOCOS process. The LOCOS process also eliminates the poly stringer problem present in prior art structures by
5304831 Low on-resistance power MOS technology April 19, 1994
A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow
5132753 Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs July 21, 1992
Transistor structure using a lightly doped drain (LDD) technique are disclosed. The present invention provides a reduced on-resistance in the LDD region, while retaining substantially all the high breakdown voltage advantage of the LDD technique. The advantage of the present invention is










 
 
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