Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Oowaki; Yukihito
Address:
Yokohama, JP
No. of patents:
68
Patents:


1 2










Patent Number Title Of Patent Date Issued
7487370 Semiconductor device and system February 3, 2009
According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which
7303965 MIS transistor and method for producing same December 4, 2007
In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer
7295456 Chain ferroelectric random access memory (CFRAM) having an intrinsic transistor connected in par November 13, 2007
A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit
7236035 Semiconductor device adapted to minimize clock skew June 26, 2007
A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a
7057917 Ferroelectric memory with an intrinsic access transistor coupled to a capacitor June 6, 2006
A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit
6993691 Series connected TC unit type ferroelectric RAM and test method thereof January 31, 2006
Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading
6906944 Ferroelectric memory June 14, 2005
A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost
6690047 MIS transistor having a large driving current and method for producing the same February 10, 2004
In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer
6671200 Ferroelectric random access memory with isolation transistors coupled between a sense amplifier December 30, 2003
A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit
6643162 Ferroelectric memory having a device responsive to current lowering November 4, 2003
A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost
6611450 Ferroelectric random access memory August 26, 2003
A ferroelectric random access memory is disclosed, which comprises a cell array including a plurality of memory cells each having a ferroelectric memory device and a cell selecting transistor connected in series to the ferroelectric storage device, and imprint restricting circuit configu
6552922 Chain-type ferroelectric random access memory (FRAM) with rewrite transistors coupled between a April 22, 2003
A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit
6545323 Semiconductor memory device including a pair of MOS transistors forming a detection circuit April 8, 2003
A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constitu
6538952 Random access memory with divided memory banks and data read/write architecture therefor March 25, 2003
A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are sub-divided into subgroups each of which
6522589 Semiconductor apparatus and mode setting method for semiconductor apparatus February 18, 2003
In a semiconductor apparatus, the first voltage detection circuit is configured to judge whether a potential of the input signal is higher or lower than a first reference potential, and output a first level signal if the potential of the input signal is judged to be higher. The second
6522569 Semiconductor memory device February 18, 2003
In a semiconductor memory device, a plurality of memory cells is coupled in series to form a memory cell block, which data is read out and data is written in, each memory cell having a cell transistor for selecting the memory cell and a ferroelectric capacitor coupled between a source an
6510071 Ferroelectric memory having memory cell array accessibility safeguards January 21, 2003
A ferroelectric memory has a memory cell array having memory cells arrayed and each constructed of a ferroelectric capacitor and a transistor, a decode circuit configured to select the memory cells of the memory cell array; a sense amplifier circuit configured to detect and amplify data
6483737 Ferroelectric memory device November 19, 2002
A ferroelectric memory device comprises a word line, first and second bit lines cross to the word line, a memory cell including a first transistor a gate of which is coupled to the word line and one of source and drain of which is coupled to the first bit line, a second transistor a gate
6473865 Apparatus comprising clock control circuit, method of controlling clock signal and device using October 29, 2002
Each delay unit is divided into two delay unit groups, the preceding stage side and the succeeding stage side. To the delay unit group in the preceding stage side, power supply voltage is supplied via a power supply terminal, and to each delay unit of the delay unit group in the succeedi
6473330 Chain type ferroelectric memory with isolation transistors coupled between a sense amplifier and October 29, 2002
A chain type ferroelectric random access memory has a memory cell unit comprising ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit
6404696 Random access memory with divided memory banks and data read/write architecture therefor June 11, 2002
A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are subdivided into subgroups each of which h
6393080 Apparatus comprising clock control circuit and device using internal clock signal synchronized t May 21, 2002
A state-holding circuit initializing circuit initializes state-holding circuit when propagation of forward pulse to the forward-pulse delay circuits in the last stage is detected. With this operation, synchronization is established in a short time from the resumption of outputting fr
6388484 Clock control circuit May 14, 2002
In this clock control circuit, clock signal CLK from a receiver is supplied to a pulse generating circuit, and the pulse generating circuit generates forward pulse, which is clock signal CLK delayed as much time as A, and pulse s which is synchronized with dock signal CLK and has a pulse
6366490 Semiconductor memory device using ferroelectric film April 2, 2002
This invention is such that, in a series-connected TC parallel-unit type ferroelectric RAM composed of a series connection of a plurality of unit cells, each unit cell being such that a ferroelectric capacitor is connected between the source and drain of a cell transistor, for instance,
6342408 Method of manufacturing semiconductor memory device January 29, 2002
A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constitu
6323525 MISFET semiconductor device having relative impurity concentration levels between layers November 27, 2001
A semiconductor device having a MISFET with an EV source/drain structure has a gate electrode formed on part of a first p-type semiconductor layer via a gate insulating film. A second n.sup.+ -type semiconductor layer is formed in the prospective source and drain regions of the first
6301185 Random access memory with divided memory banks and data read/write architecture therefor October 9, 2001
A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are sub-divided into subgroups each of which
6278165 MIS transistor having a large driving current and method for producing the same August 21, 2001
In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer
6211686 Evaluation apparatus and fabrication system for semiconductor April 3, 2001
The present invention comprises a SCM measuring apparatus and a control section. A control section adjusts shape data of a probe tip initially inputted based on SCM measurement for a standard specimen and a simulated result by the measuring apparatus, and then performs the SCM measuremen
6177811 Semiconductor integrated circuit device January 23, 2001
A semiconductor integrated circuit device includes a semiconductor substrate, a MOS transistor formed on the semiconductor substrate and having a first gate, wherein a first signal supplied to the first gate and a second signal supplied to a substrate region corresponding to the semi
6147918 Dynamic semiconductor memory device having an improved sense amplifier layout arrangement November 14, 2000
A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connecte
6130461 Semiconductor memory device October 10, 2000
A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constitu
6118721 Random access memory with divided memory banks and data read/write architecture therefor September 12, 2000
A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are subdivided into subgroups each of which h
6084453 Clock converting circuit July 4, 2000
A cycle measuring circuit 3 measures a cycle of an external clock signal, which is approximately m times a unit time. A number converting circuit 5 and a time converting circuit 7 cooperate, generating a pulse signal delayed by m/2.sup.K times the unit time, or by 1/2.sup.K times the cyc
6054371 Method of manufacturing a semiconductor device by detachably mounting substrates to a holder boa April 25, 2000
Disclosed is a method of manufacturing a semiconductor device, comprising the step of detachably mounting a plurality of semiconductor substrates to a first holder board so as to form a complex semiconductor substrate, and the step of subjecting the plural semiconductor substrates includ
6040610 Semiconductor device March 21, 2000
A semiconductor device comprises a chip including a MISFET having a source and a drain, in which one of the source and the drain is connected to a second current supply node, an impedance element having a first terminal connected to the other of the source and the drain and a second term
5969998 MOS semiconductor device with memory cells each having storage capacitor and transfer transistor October 19, 1999
A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode
5953246 Semiconductor memory device such as a DRAM capable of holding data without refresh September 14, 1999
A semiconductor memory device comprises a plurality of word lines, a plurality of bit lines intersecting the word lines, and memory cells selectively arranged at intersections of the word lines and the bit lines, and each consisting of a transistor and a capacitor, the transistor having
5933380 Semiconductor memory device having a multilayered bitline structure with respective wiring layer August 3, 1999
A semiconductor memory device includes a memory cell array having a plurality of memory cells, the memory cell array being divided into a plurality of blocks, a plurality first bitlines arranged in each of the blocks, the plurality of first bitlines forming a plurality of first bitli
5895956 Semiconductor memory device April 20, 1999
A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constitu
5892724 NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-ope April 6, 1999
A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell
5892247 Semiconductor device and a manufacturing method thereof April 6, 1999
The semiconductor device comprises a substrate, a first conductive layer formed on the substrate with a first insulating layer inserted therebetween, thereby to constitute a first gate electrode, a second conductive layer selectively formed on the first gate electrode with a second i
5870339 MOS semiconductor device with memory cells each having storage capacitor and transfer transistor February 9, 1999
A MOS dynamic random access memory includes a plurality of pairs of bit lines, and word lines transverse to the bit lines to define cross points, at which an array of memory cells are arranged. Each cell has a storage capacitor and a transfer gate MOS transistor having a gate electrode
5867040 Integrated circuit with stacked sub-circuits between Vcc and ground so as to conserve power and February 2, 1999
The semiconductor integrated circuit device of the present invention includes a plurality of integrated circuits. The scheduling circuit selects an arbitrary number of integrated circuit from the plurality of integrated circuits, and connects the selected integrated circuits between
5864508 Dynamic random-access memory with high-speed word-line driver circuit January 26, 1999
A random-access memory includes an array of rows and columns of memory cells. Word lines are associated with rows of memory cells, bit lines lines are with columns of memory cells. A row decoder and a core control circuit are connected to the word lines. A column decoder and a sense
5859805 Dynamic semiconductor memory device having an improved sense amplifier layout arrangement January 12, 1999
A dynamic semiconductor memory device is made up of a plurality of dynamic memory cells arrayed along a plurality of bit line pairs, and a plurality of dynamic sense amplifiers associated with the plurality of bit line pairs, each sense amplifier having a pair of MOS transistors connecte
5838038 Dynamic random access memory device with the combined open/folded bit-line pair arrangement November 17, 1998
A semiconductor memory device includes active regions arranged on a semiconductor substrate such that those of the active regions which are adjacent in the word line direction deviate in the bit line direction, MOS transistors respectively formed in the active regions and each having a
5831928 Semiconductor memory device including a plurality of dynamic memory cells connected in series November 3, 1998
A semiconductor device includes a memory cell array having memory cells arranged in a matrix form, a plurality of bit lines for communicating information to the memory cells, and a plurality of word lines crossing the bit lines to select among the memory cells, a plurality of sense a
5761109 Semiconductor memory device having folded bit line array and an open bit line array with imbalan June 2, 1998
A dynamic semiconductor memory device according to the present invention comprises at least first and second memory cell arrays having a plurality of memory cells selectively arranged at respective intersections of a plurality of word lines and a plurality of bit lines, a first sense
5717625 Semiconductor memory device February 10, 1998
In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading
1 2










 
 
  Recently Added Patents
Semiconductor device and manufacturing method thereof
Method and apparatus for organizing segments of media assets and determining relevance of segments to a query
Radio frequency splitter
Mobile advertising and compensation-verification system
Techniques for image segment accumulation in document rendering
Computing device with improved user interface for applications
Golf club cover
  Randomly Featured Patents
Roll storage module and method for its operation
Door for a motor vehicle
3-alkoxycarbonyl-thiadiazinones
Catalyst for ozone decomposition
Single handle mixing valve with an improved ball valve
Apparatus and method for use in a well bore
Procedure for determining at least one misfiring cylinder of a combustion engine, control unit and motor vehicle drive train
Simplified in-vitro interferon production
Plug-flow regeneration process
Acidic cleaning agent with a scouring action