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Okumura; Yoshiki
Kawasaki, JP
No. of patents:

Patent Number Title Of Patent Date Issued
7480691 Arithmetic device for multiple precision arithmetic for Montgomery multiplication residue arithm January 20, 2009
In an arithmetic device which performs a multiplication of a multiplicand A and a multiplier B expressed by bit patterns using a secondary Booth algorithm, an encoder selects a partial product indicating -A when the value of i specifying three consecutive bits of B is 0, and selects a
7159058 State indicating information setting circuit and status bit setting circuit January 2, 2007
A state indicating information setting circuit and a status bit setting circuit are responsive to detection of a predetermined state by a predetermined state detecting part for setting predetermined state indicating information and, then, appropriately resetting the detection state i
7096406 Memory controller for multilevel cell memory August 22, 2006
A N-level cell memory controlled by the memory controller of the invention have an internal configuration in which the plurality of data input/output terminals connected to the second data bus are separated into first through Mth data input/output terminal groups, such that there is

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