| Patent Number |
Title Of Patent |
Date Issued |
| 7465956 |
Stacked organic memory devices and methods of operating and fabricating |
December 16, 2008 |
| The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more |
| 7012013 |
Dielectric pattern formation for organic electronic devices |
March 14, 2006 |
| Methods and systems are provided for patterning a non conductive dielectric on a surface of a conductive polymer. The conductive polymer can be part of an organic memory cell. Hydrogen ions created form molecular hydrogen being exposed to short wave length radiation, are employed as |
| 6979837 |
Stacked organic memory devices and methods of operating and fabricating |
December 27, 2005 |
| The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more |
| 6977389 |
Planar polymer memory device |
December 20, 2005 |
| The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and |
| 6893895 |
CuS formation by anodic sulfide passivation of copper surface |
May 17, 2005 |
| Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve passivating a portion of a copper containing electrode to form a copper sulfide layer in an electrochemical cell by applying a current through a passivation solution |
| 6884735 |
Materials and methods for sublithographic patterning of gate structures in integrated circuit de |
April 26, 2005 |
| An integrated circuit fabrication process including exposing a photoresist layer and providing a hydrophilic layer above the photoresist layer. The photoresist layer is exposed to a pattern of electromagnetic energy. The polymers in the hydrophilic layer can diffuse into the photoresist |
| 6870183 |
Stacked organic memory devices and methods of operating and fabricating |
March 22, 2005 |
| The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more |
| 6852586 |
Self assembly of conducting polymer for formation of polymer memory cell |
February 8, 2005 |
| The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer self assembles relative to a conductive electrode. The process affords self-assembly such that |
| 6815359 |
Process for improving the etch stability of ultra-thin photoresist |
November 9, 2004 |
| An integrated circuit fabrication process is disclosed herein. The process includes exposing a photoresist layer to a plasma, and transforming the top surface and the side surfaces of the photoresist layer to form a hardened surface. The process further includes etching the substrate in |
| 6787458 |
Polymer memory device formed in via opening |
September 7, 2004 |
| One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, form |
| 6774365 |
SEM inspection and analysis of patterned photoresist features |
August 10, 2004 |
| A process for improving the accuracy of critical dimension measurements of features patterned on a photoresist layer using a scanning electron microscope (SEM) is disclosed herein. The process includes providing an electron beam to the photoresist layer and transforming the surface of th |
| 6767693 |
Materials and methods for sub-lithographic patterning of contact, via, and trench structures in |
July 27, 2004 |
| An integrated circuit fabrication process including exposing a photoresist layer and providing a hydrophilic layer above the photoresist layer. The photoresist layer is exposed to a pattern of electromagnetic energy. The polymers in the hydrophilic layer can diffuse into the photoresist |
| 6764808 |
Self-aligned pattern formation using wavelenghts |
July 20, 2004 |
| An integrated circuit fabrication process for patterning features at sub-lithographic dimensions is disclosed herein. The process includes sequentially exposing a of a film of arylalkoxysilane with a photobase generator, and catalytic amount of water coated on top of a conventional l |
| 6753247 |
Method(s) facilitating formation of memory cell(s) and patterned conductive |
June 22, 2004 |
| A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is appl |
| 6716571 |
Selective photoresist hardening to facilitate lateral trimming |
April 6, 2004 |
| A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch |
| 6653231 |
Process for reducing the critical dimensions of integrated circuit device features |
November 25, 2003 |
| A process for forming sub-lithographic features in an integrated circuit is disclosed herein. A process for enhancing the etch trimmability and the etch stability of features patterned on a photoresist layer is also disclosed herein. The process includes curing a photoresist layer after |
| 6630288 |
Process for forming sub-lithographic photoresist features by modification of the photoresist sur |
October 7, 2003 |
| A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch |
| 6589713 |
Process for reducing the pitch of contact holes, vias, and trench structures in integrated circu |
July 8, 2003 |
| An integrated circuit fabrication process to pattern features having reduced pitch is disclosed herein. The process includes reducing the width of a developed exposed area of a patterned photoresist layer provided over a substrate before patterning the substrate. The process further incl |
| 6589709 |
Process for preventing deformation of patterned photoresist features |
July 8, 2003 |
| A process for preventing deformation of patterned photoresist features during integrated circuit fabrication is disclosed herein. The process includes stabilizing the patterned photoresist features by a flood electron beam before one or more etch processes. The stabilized patterned p |
| 6518175 |
Process for reducing critical dimensions of contact holes, vias, and trench structures in integr |
February 11, 2003 |
| An integrated circuit fabrication process to pattern reduced feature size is disclosed herein. The process includes reducing the width of a patterned area of a patterned photoresist layer provided over a substrate before patterning the substrate. The patterned area is representative of a |
| 6475904 |
Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials |
November 5, 2002 |
| A damascene structure and method of making the same in a low k dielectric material employs an imageable layer in which the damascene pattern is provided. The imageable layer is an alicyclic polymer into which silicon is incorporated by liquid silylation, for example. The silicon-rich |
| 6127089 |
Interconnect structure with low k dielectric materials and method of making the same with single |
October 3, 2000 |
| A damascene structure and method of making the same in a low k dielectric material employs an imageable layer in which the damascene pattern is provided. The imageable layer is a convertible layer that upon exposure to the plasma etch that etches the low k dielectric material, converts t |
