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Okamoto; Fuyuki
Tokyo, JP
No. of patents:

Patent Number Title Of Patent Date Issued
6833869 Solid-state imaging device with voltage followers formed by selected row transistors and column December 21, 2004
A solid-state imaging device has an array of pixels arranged in a matrix pattern of rows and columns. Each pixel has a photodiode for developing a voltage corresponding to light incident thereon, a first amplifying transistor for amplifying the voltage and a row select switching tran
6784932 Hierarchical pixel readout multiplexer with switched capacitors for cancelling buffer offsets August 31, 2004
A hierarchical readout circuit includes a plurality of first capacitors for respectively interposed in a plurality of lines at which individual voltages are developed. Before the individual voltages appear at the lines, the inputs of the first capacitors are simultaneously biased at
6580063 Solid state imaging device having high output signal pain June 17, 2003
The solid state imaging device comprising active pixels has a structure in which transistors for amplification 103 and 113 which amplify an output signal of a photodiode 101 composing a photoelectric conversion portion are constituted as a voltage follower. By using the transistors for
6410900 Solid-state image sensor and method of driving the same June 25, 2002
There is provided a solid-state image sensor including (a) a plurality of pixels arranged in a matrix in a photoelectric transfer region, (b) at least one movement-detector located in the photoelectric transfer region, (c) a first Y-scanner making successive access to the pixels in rows
6313458 Gain-adjustable photoreceiver circuit with photoelectric converter and amplifier November 6, 2001
A photoreceiver circuit includes (a) a photoelectric conversion element for converting incident light to a current, (b) an analog voltage amplifier circuit for amplifying a voltage corresponding to the current of the photoelectric conversion element and for producing an amplified voltage
5546035 Latch circuit having a logical operation function August 13, 1996
A latch circuit with an NAND function comprises a three-input NAND gate circuit, a first transfer gate connected between a first input terminal and a first input of the NAND gate circuit, a second transfer gate connected between a second input terminal and a second input of the NAND
5424968 Priority encoder and floating-point adder-substractor June 13, 1995
A priority encoder for a normalization at a floating-point addition of subtraction for encoding a leading zero number of a difference of two input binary numbers within an error of -1, and a floating-point adder-subtractor using this priority encoder. The priority encoder includes a
5369607 Floating-point and fixed-point addition-subtraction assembly November 29, 1994
Apparatus for use in a floating-point and fixed-point adder-subtractor assembly. The apparatus includes a comparator and selector circuit disposed prior to an adder-subtracter for determining a larger and smaller operand prior to the addition and subtraction operation. The comparator
5309385 Vector division processing method and system May 3, 1994
In vector dividing the process employing convergence division method, the process steps are performed for performing pipeline processing of multiplying operation of the dividend and a first convergence factor in a speed of one clock cycle per one element to generate a first intermediate
5303174 Floating pointing arithmetic operation system April 12, 1994
In a floating point arithmetic addition/subtraction system which is configured to receive a pair of input operands of floating point data including its mantissa part expressed in an absolute value so as to execute an addition/subtraction and which includes a mantissa adder, a normali
5084835 Method and apparatus for absolute value summation and subtraction January 28, 1992
In an absolute value subtraction processing of .vertline.X-Y.vertline., carry generation and propagation functions and group carry generation and propagation functions are first generated. Then, a carry is calculated at the most significant bit in the summation of a first operand and a

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