Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Ohhashi; Masahide
Address:
Sagamihara, JP
No. of patents:
5
Patents:












Patent Number Title Of Patent Date Issued
4592007 Full adder using complementary MOSFETs May 27, 1986
The invention provides a full adder having a logic circuit which has an inverter and a selector circuit, a logic circuit which has an inverter and a selector circuit, and a logic circuit which has a selector circuit and an inverter so as to produce a sum output signal S and a carry outpu
4573137 Adder circuit February 25, 1986
In an adder circuit in which the input data is divided into a plurality of bit blocks each consisting of a plurality of bits for parallel data processing, two adder sections with the carry inputs thereto respectively set to logic "0" and "1" are provided for each of the blocks other than
4507749 Two's complement multiplier circuit March 26, 1985
A multiplication circuit includes a multiplying unit for multiplying a signed multiplier X represented in terms of the two's complement of n bits by a signed multiplicand Y represented in terms of two's complement of n bits to generate a signed multiplication output data of (2n-1) bits
4498178 Data error correction circuit February 5, 1985
A data error correction circuit is provided, which receives input data having check bit data added thereto, the input data being divided by a generator polynomial G(x) in terms of the modulo 2 and multiplied by a correction polynomial M(x) in terms of modulo 2. An error in the input
4363107 Binary multiplication cell circuit December 7, 1982
A binary multiplication cell circuit suitable for a MOS transistor integrated circuit. The cell circuit has a NOR circuit for obtaining a partial product of one binary digit of a multiplicand and one binary digit of a multiplier and a full adder for obtaining result of multiplication










 
 
  Recently Added Patents
Resistive memory element sensing using averaging
Compositions of quaternary ammonium compounds containing bioavailability enhancers
Late loading rich media
5-HT.sub.3 receptor modulators, methods of making, and use thereof
Reliable and accurate usage detection of a software application
Method and apparatus for detection of LVDT core fallout condition
System and method for managing self-refresh in a multi-rank memory
  Randomly Featured Patents
Remaining ink level detection method and inkjet printing apparatus
Preparation and use of sialylated glycoforms of soluble complement receptor 1 (CR1)
Indication of scenes on a projector programmed on the basis of scenes
Open pool forming a reservoir for liquid especially swimming pool, of the out-of-ground type
Method for fabricating a pixel structure and the pixel structure
Log trailer load extension axle assembly
Manufacturing method and system and associated rolls of sheets with alternating cuts and pre-cuts
Cleaning method for electrophotography and means therefor
Methods for identifying semiconductor wafer with bar code pattern thereon and methods for manufacturing semiconductor device
Antioxidant compositions extracted from olives and olive by-products