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Ohhashi; Masahide
Sagamihara, JP
No. of patents:

Patent Number Title Of Patent Date Issued
4592007 Full adder using complementary MOSFETs May 27, 1986
The invention provides a full adder having a logic circuit which has an inverter and a selector circuit, a logic circuit which has an inverter and a selector circuit, and a logic circuit which has a selector circuit and an inverter so as to produce a sum output signal S and a carry outpu
4573137 Adder circuit February 25, 1986
In an adder circuit in which the input data is divided into a plurality of bit blocks each consisting of a plurality of bits for parallel data processing, two adder sections with the carry inputs thereto respectively set to logic "0" and "1" are provided for each of the blocks other than
4507749 Two's complement multiplier circuit March 26, 1985
A multiplication circuit includes a multiplying unit for multiplying a signed multiplier X represented in terms of the two's complement of n bits by a signed multiplicand Y represented in terms of two's complement of n bits to generate a signed multiplication output data of (2n-1) bits
4498178 Data error correction circuit February 5, 1985
A data error correction circuit is provided, which receives input data having check bit data added thereto, the input data being divided by a generator polynomial G(x) in terms of the modulo 2 and multiplied by a correction polynomial M(x) in terms of modulo 2. An error in the input
4363107 Binary multiplication cell circuit December 7, 1982
A binary multiplication cell circuit suitable for a MOS transistor integrated circuit. The cell circuit has a NOR circuit for obtaining a partial product of one binary digit of a multiplicand and one binary digit of a multiplier and a full adder for obtaining result of multiplication

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