| Patent Number |
Title Of Patent |
Date Issued |
| 6981187 |
Test mode for a self-refreshed SRAM with DRAM memory cells |
December 27, 2005 |
| A self-refreshing SRAM with internal DRAM memory cells is provided with a test mode enable circuit for testing the real refresh time of the internal SRAM memory cells and for determining the maximum refresh capability of the internal DRAM memory cells. The self-refreshing DRAM includes a |
| 6735142 |
Power-up control circuit with a power-saving mode of operation |
May 11, 2004 |
| A power-up control circuit has three components including a normal power-supply voltage level detection section, a special command section for detecting a deep-sleep enable input signal, and an output driver section that logically combines the output signal of the normal power-supply |
| 6721210 |
Voltage boosting circuit for a low power semiconductor memory |
April 13, 2004 |
| An improved voltage boosting circuit operates entirely from a single, common VCC voltage supply. An NMOS pass transistor has a gate input terminal to which is connected a gate boost capacitor and a PMOS precharge circuit. A drain terminal of the NMOS pass transistor is connected to a |
| 6643216 |
Asynchronous queuing circuit for DRAM external RAS accesses |
November 4, 2003 |
| A method and queuing circuit are provided for storing asynchronous external RAS access requests and for executing corresponding RAS cycles. When no current external access RAS cycle is currently underway a first request latch or similar storage element is set in response to an initial ac |
