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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Numata; Hideaki
Address:
Tokyo, JP
No. of patents:
10
Patents:












Patent Number Title Of Patent Date Issued
8253124 Semiconductor element August 28, 2012
This invention provides a semiconductor element which uses a plurality of carbon nanotubes as a current path, can reduce contact resistance of its electrode contact part, and has excellent electrical characteristics. This semiconductor element is characterized in that the semiconductor
8238135 MRAM utilizing free layer having fixed magnetization regions with larger damping coefficient tha August 7, 2012
A magnetic recording layer 10 of an MRAM has a first magnetization fixed region 11, a second magnetization fixed region 12 and a magnetization switching region 13. The magnetization switching region 13 has reversible magnetization and overlaps with a pinned layer. The first magnetization
7929342 Magnetic memory cell, magnetic random access memory, and data read/write method for magnetic ran April 19, 2011
The present invention provides a new data writing method for an MRAM which can suppress deterioration of a tunnel barrier layer. A magnetic memory cell 1 has a magnetic recording layer 10 and a pinned layer 30 connected to the magnetic recording layer 10 through a non-magnetic layer
7177179 Magnetic memory, and its operating method February 13, 2007
A technology for eliminating the defects in a tunnel insulation film of magnetic tunnel junction and for suppressing generation of a defective bit in an MRAM using magnetic tunnel junction in a memory. The magnetic memory includes a substrate, an interlayer insulation film covering the
7126201 Magnetic random access memory October 24, 2006
A technique is provided in which an offset magnetic field of a memory cell of a MRAM is reduced more effectively. The MRAM of the present invention is composed of a free layer (11) which has a reversible free spontaneous magnetization, a fixed layer (6) which has fixed spontaneous ma
6703249 Method of fabricating magnetic random access memory operating based on tunnel magnetroresistance March 9, 2004
A method of manufacturing a magnetic random access memory for excluding stress-induced defects in memory cells. The method is composed of forming a first magnetic film over a substrate, forming a tunnel insulating film on the first magnetic film such that the tunnel insulating film has a
6462982 Magnetic random access memory having voltage control circuitry for maintaining sense lines at co October 8, 2002
A matrix array of memory cells are located on intersections of word lines and sense lines. Each memory cell has a magnetoresistance element and a switching element which establishes a connection between a corresponding sense line and the magnetoresistance element when a corresponding wor
6462981 Magnetic random access memory October 8, 2002
A matrix array of memory cells are located on intersections of word lines and sense lines. Each memory cell includes a magnetoresistance element and a switching element which establishes a resistive connection between a corresponding sense line and the magnetoresistance element when a
6341084 Magnetic random access memory circuit January 22, 2002
In a magnetic random access memory circuit, the potential of all sense lines 121 to 124 are equalized, and the potential of all not-selected word lines 133, 135, 136 are equalized and the selected word line 134 is grounded so that a previously charged capacitor 114 is discharged by a
6191972 Magnetic random access memory circuit February 20, 2001
A magnetic random access memory circuit comprises first and second row decoders receiving a part of a given address, first and second column decoders receiving the other part of a given address, a plurality of pairs of sense lines connected between output terminals of the first row decod










 
 
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