| Patent Number |
Title Of Patent |
Date Issued |
| 7599431 |
Combined decision feedback equalization and linear equalization |
October 6, 2009 |
| A communication system includes a transmitter, a communication channel, and a receiver. The transmitter includes a pre-emphasis module, a summing module, a line driver, and a decision feedback pre-emphasis (DFP) module to produce a pre-emphasized serial stream of data based on a comm |
| 7376199 |
Approach for adjusting the phase of channel-bonded data |
May 20, 2008 |
| An example embodiment is directed to an arrangement and method for phase-aligning digital data to be sent by transmit-data modules over respectively-situated serial links. A reference clock signal is communicatively coupled to each transmit-data module, each transmit-data module havi |
| 7265640 |
Circuit approach for common mode control in high-frequency clocks |
September 4, 2007 |
| An example embodiment is directed to shifting the common mode voltage of an analog oscillation stage toward a center line between the upper and lower power-supply rails of a first digital circuit. The first digital circuit has a digital input port adapted to respond to signal transitions |
| 7106099 |
Decision-feedback equalization clocking apparatus and method |
September 12, 2006 |
| A decision feedback equalization ("DFE") technique is suitable for use in a serializer-deserializer ("SERDES") receiver in an integrated circuit (IC). The IC has a summing node coupled to a return-to-zero ("RTZ") data latch register. The RTZ data latch register has a first ("even") serie |
| 7091773 |
Limiting circuit with level limited feedback |
August 15, 2006 |
| A limiting circuit includes an input transconductance stage, an output transconductance stage, a feedback transconductance stage, first and second resistive loads, and a level limiting circuit. The input transconductance stage is operably coupled to convert an input voltage signal in |
| 7084683 |
High-speed differential flip-flop with common-mode stabilization |
August 1, 2006 |
| A differential flip-flop (400) has an output stage (402) with first and second input terminals (X1, X2), first and second output terminals (Q, Qb), a first voltage supply terminal (Vss), a first transistor (435) having a first current-handling terminal connected to the first output t |
| 7058120 |
Integrated high-speed serial-to-parallel and parallel-to-serial transceiver |
June 6, 2006 |
| A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation wit |
| 7012985 |
Frequency division of an oscillating signal involving a divisor fraction |
March 14, 2006 |
| A frequency-divider circuit performs a division operation using a divisor that can include a fraction. In one such embodiment, a first divider module includes a divider circuit that operates to divide the frequency of an input clock signal and a phase-quadrature circuit. The first di |
| 6927608 |
Low power low voltage differential signaling driver |
August 9, 2005 |
| A low power LVDS driver includes a switchable current module, a source termination circuit, a transistor section, and a load current source. The switchable current module is operably coupled to produce a first current when a differential input signal is in a first state and to produce a |
| 6819156 |
High-speed differential flip-flop |
November 16, 2004 |
| Described are high-speed differential flip-flops. A flip-flop in accordance with one embodiment incorporates some combinational logic, eliminating the need for separate combinational logic when the flip-flop is employed in certain circuit configurations. A flip-flop in accordance with an |
| 6784822 |
Method and circuit for folded analog-to-digital converter (ADC) using frequency detectors and ti |
August 31, 2004 |
| A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A |
| 6677879 |
Method and circuit for folded analog-to-digital converter (ADC) using frequency detectors and ti |
January 13, 2004 |
| A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A |
| 6621307 |
Method and circuit for determining frequency and time variations between electronic signals |
September 16, 2003 |
| A method and circuit for determining variation between an input clock signal (CLK0) and a reference clock signal (REFCLK) is provided. A plurality of time shifted input clock signals (CLK0, CLK1, . . . , CLK09) can be generated from a single input clock signal (CLK0). The plurality of |
| 6617887 |
Differential comparator with offset correction |
September 9, 2003 |
| A differential comparator having offset correction and common mode control for providing stable op amp output that changes only due to the original inputs coming into the comparator. The difference comparator has increased common-mode difference tolerance, and large op-amp offset toleran |
| 6611218 |
Transmitter with multiphase data combiner for parallel to serial data conversion |
August 26, 2003 |
| Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bit |
| 6586964 |
Differential termination with calibration for differential signaling |
July 1, 2003 |
| A system for calibrating an adjustable termination resistor for a low voltage differential signaling (LVDS) system is provided. The system includes an adjustable termination resistor located on a chip and a reference termination resistor located off the chip. A bias circuit coupled t |
| 6553443 |
Method and apparatus for prioritizing interrupts in a communication system |
April 22, 2003 |
| A communications system includes a communications channel, a first processing unit; and interface unit, and an interrupt controller. The first processing unit is adapted to monitor the communications channel and provide a plurality of status bits. The interface unit includes an inter |
| 6535030 |
Differential comparator with offset correction |
March 18, 2003 |
| A differential comparator having offset correction and common mode control providing stable op amp output that changes only due to the original inputs coming into the comparator. The difference comparator has increased common-mode difference tolerance, and large op-amp offset tolerance, |
| 5764581 |
Dynamic ram with two-transistor cell |
June 9, 1998 |
| A dynamic RAM having two-transistor memory cells includes a top array of memory cells and a bottom array of memory cells, with a sense amplifier disposed between the two halves. The memory cells in each column of the top half are coupled to respective Bit.sub.-- Plus lines, and the memor |
| 5638440 |
Protection circuit for telephone systems |
June 10, 1997 |
| A power-cross detection circuit includes a zero crossing detection circuit for detecting a first zero crossing of the current from a first positive half-cycle to a first negative half-cycle, a second zero crossing of the current from a second positive half-cycle to a second negative half |
| 5420815 |
Digital multiplication and accumulation system |
May 30, 1995 |
| A multiplication system performs a series of multiplications and accumulations of plural pairs of first and second operands. The system includes first and second buses, a memory for storing the plural pairs of first and second operands, and a read buffer coupled to the memory for seq |
| 5347480 |
Digital signal processing apparatus |
September 13, 1994 |
| An apparatus for processing a received signal according to a digital signal processing algorithm having a multiplier and a limit and quantization circuit appropriately connected within the apparatus to permit operation of the multiplier and the limit and quantization circuit in parallel |
| 5282153 |
Arithmetic logic unit |
January 25, 1994 |
| An arithmetic logic unit includes first and second buses for efficient operations upon multiple-bit operands. The arithmetic logic unit includes, in addition to the first and second buses, a shift register having an input coupled to the first bus and an output, a summer having a first |
| 5272654 |
System for converting a floating point signed magnitude binary number to a two's complement bina |
December 21, 1993 |
| A system for converting a floating point n-bit signed magnitude binary number to a fixed point two's complement binary number having m bits wherein m is greater than n, first converts the n bit signed magnitude binary number to a corresponding n-bit two's complement binary number. Th |
