| Patent Number |
Title Of Patent |
Date Issued |
| 6657459 |
Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and i |
December 2, 2003 |
| A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pas |
| 6574154 |
Data transmitter |
June 3, 2003 |
| A large difference in the lengths of the passages or a large difference in the load capacitances inclusive of parasitic elements of parallel data wirings can cause differences in the propagation time of data on the parallel data wirings. The invention provides a simultaneous arrival |
| 6462580 |
Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and i |
October 8, 2002 |
| The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of br |
| 6359815 |
Data transmitter |
March 19, 2002 |
| When there is a difference in the lengths of the passages among the parallel data wirings or a difference in the load capacitances inclusive of parasitic elements, a difference in the propagation time among the data becomes no longer negligible. At the time of transmitting data at high |
| 6271687 |
Sense amplifier circuit |
August 7, 2001 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
| 6172532 |
Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and i |
January 9, 2001 |
| The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of |
| 6160275 |
Semiconductor gate array device |
December 12, 2000 |
| In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within |
| 6046609 |
Sense amplifier circuit |
April 4, 2000 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
| 5963483 |
Synchronous memory unit |
October 5, 1999 |
| A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the |
| 5880602 |
Input and output buffer circuit |
March 9, 1999 |
| An input and output buffer circuit which is contained in a first circuit operated on a first power source of a first voltage level Vcc1 and is permitted to connect to a second circuit operated on a second power source of a second voltage level Vcc2 higher than the first voltage level Vcc |
| 5854562 |
Sense amplifier circuit |
December 29, 1998 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
| 5677641 |
Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and i |
October 14, 1997 |
| The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of |
| 5666072 |
Semiconductor integrated circuit device having bipolar transistor and field effect transistor |
September 9, 1997 |
| A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its |
| 5663659 |
Semiconductor integrated circuit device comprising CMOS transistors and differentiator |
September 2, 1997 |
| The semiconductor IC device has a circuit arrangement constituted by a first CMOS logic gate having input and output terminals, and a second CMOS logic gate which performs the same logic operation as that of the first CMOS logic gate and which has an input terminal connected to the input |
| 5614848 |
High-speed semiconductor integrated circuit device composed of CMOS and bipolar transistors |
March 25, 1997 |
| The semiconductor IC device has a circuit arrangement in which one or more of the circuits, such as on a single substrate, include a totem-pole series connection of bipolar transistors which are driven by arrangements of complementary MOS circuits in a manner such that high-speed log |
| 5604417 |
Semiconductor integrated circuit device |
February 18, 1997 |
| The device has, on a single substrate, plural internal circuits, plural input circuits for receiving external input signals and outputting the same to the internal circuit, and plural output circuits for receiving signals outputted from the internal circuits and externally outputting the |
| 5600268 |
Gate circuit of combined field-effect and bipolar transistors |
February 4, 1997 |
| A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar |
| 5412262 |
Semiconductor integrated circuit device having plurality of supply potential lines connected the |
May 2, 1995 |
| In a system wherein a plurality of semiconductor integrated circuit devices are coexistent and wherein a plurality of supply potential lines are laid, the main power sources of a TTL interface LSI and an ECL interface LSI are shared so as to reduce the number of supply potential lines. B |
| 5378941 |
Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device |
January 3, 1995 |
| A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to |
| 5377136 |
Semiconductor integrated circuit device with built-in memory circuit group |
December 27, 1994 |
| A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by |
| 5313116 |
Semiconductor integrated circuit device having bipolar transistor and field effect transistor |
May 17, 1994 |
| A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its |
| 5265045 |
Semiconductor integrated circuit device with built-in memory circuit group |
November 23, 1993 |
| A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by |
| 5239212 |
Gate circuit of combined field-effect and bipolar transistors with an improved discharge arrange |
August 24, 1993 |
| A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar |
| 5059821 |
Bi-CMOS driver with two CMOS predrivers having different switching thresholds |
October 22, 1991 |
| A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5V. The logic circuit includes a bipolar transistor having a base and its |
| 4890017 |
CMOS-BiCMOS gate circuit |
December 26, 1989 |
| A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar |
| 4829201 |
Gate circuit of combined field-effect and bipolar transistors |
May 9, 1989 |
| A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar |
| 4719373 |
Gate circuit of combined field-effect and bipolar transistors |
January 12, 1988 |
| A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar |
| 4589007 |
Semiconductor integrated circuit device |
May 13, 1986 |
| A semiconductor integrated circuit device is disclosed. A plurality of unit cells, each having at least a basic transistor device formed on one main surface of a semiconductor substrate, are arranged in a line to form a unit cell line. At least two of such unit cell lines are arranged ad |
| 4237543 |
Microprocessor controlled display system |
December 2, 1980 |
| A display system for displaying information in response to an input video signal comprises a data control unit including a microprocessor and a microprogram memory for storing a program for the microprocessor, a refresh memory unit connected to the data control unit through an address |
