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Inventor:
Niijima; Hideto
Address:
Tokyo, JP
No. of patents:
11
Patents:












Patent Number Title Of Patent Date Issued
5928315 Apparatus and method for calculating B.sup.c (mod n) July 27, 1999
Apparatus method for calculating the remainder of B.sup.C modulo n at high speed with minimum hardware resources, while securing the safety of the key in a cryptographic system. The apparatus comprises circuitry including registers for executing an initial and normal cycles, cumulating a
5923839 Data storage system, data transfer method, and data reconstruction method July 13, 1999
A data storage system is provided having a faster data transfer rate and reduced complexity though improved control of timing. The data storage system has a plurality of storage devices and a plurality of data buses through which data are transferred. An input/output unit interleaves a
5844910 Flash-erase-type nonvolatile semiconductor storage device December 1, 1998
An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag
5787493 Control method and apparatus for direct execution of a program on an external apparatus using a July 28, 1998
With the present invention, the page table of the program code non-continuously placed in an external storage device using randomly accessible and rewritable memory is built into an executable sequence in a virtual address space of the CPU according to the execution order. By referri
5734816 Nonvolatile memory with flash erase capability March 31, 1998
A nonvolatile memory with flash erase capability includes a plurality of clusters each having a plurality of sectors, each of the sectors holding the attribute information for identification. A cluster information sector is placed at the top of a cluster to which it belongs. A data secto
5598370 Nonvolatile memory with cluster-erase flash capability and solid state file apparatus using the January 28, 1997
A nonvolatile memory-with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence numbe
5546402 Flash-erase-type nonvolatile semiconductor storage device August 13, 1996
An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag
5524230 External information storage system with a semiconductor memory June 4, 1996
To provide an external storage system using a semiconductor memory in which the data reading and writing between the host CPU can be processed faster than the conventional magnetic disk, and only a particular sector is not frequently written and erased so that the whole memory is effecti
5509018 Flash-erase-type nonvolatile semiconductor storage device April 16, 1996
An array of memory cells is physically divided into a data area and a tag area so that respective parts of the two areas share a word line but can be separately erased en bloc. The data area and tag area sharing one word line constitute a single logical unit. In the logical unit, the tag
5457658 Nonvolatile memory with cluster-erase flash capability and solid state file apparatus using the October 10, 1995
A nonvolatile memory with cluster-erase flash capability. A cluster information sector is included in each of N clusters, the cluster information sector of each cluster being written with the sequence number assigned to the cluster so that no two clusters have the same sequence numbe
5448733 Data search and compression device and method for searching and compressing repeating data September 5, 1995
This is a variable length data search apparatus which uses a latch, added to each word of a cell array. In this apparatus, the search operation is self controlled by using the previous matching signals stored in the latches. A character string (ABCA), from a data string (BABCABB . . . ),










 
 
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