| Patent Number |
Title Of Patent |
Date Issued |
| 6161162 |
Multiprocessor system for enabling shared access to a memory |
December 12, 2000 |
| A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are controlled by an arbitration circuit which allows one CPU to always have the highest priority. The primary CPU may or may not be the hi |
| 6023735 |
Expansion module including programmable chip selects |
February 8, 2000 |
| The present invention relates to a computer system and more particularly to a computer system which allows option controller cards for various input/output (I/O) devices to be added on the motherboard at minimum cost. |
| 6009495 |
Protected address range in an electrically erasable programmable read only memory |
December 28, 1999 |
| An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the prote |
| 5999991 |
Programmably selectable addresses for expansion cards for a motherboard |
December 7, 1999 |
| The present invention relates to a computer system and more particularly to a computer system which allows option controller cards for various input/output (I/O) devices to be added on the motherboard at minimum cost. |
| 5987618 |
Programmable hardware timer including two programmable hardware downcounters wherein the second |
November 16, 1999 |
| A programmable hardware timer provides a relatively consistently measure of predetermined time intervals over a relatively wide range of performance levels. The programmable hardware timer includes a downcounter, driven by a predetermined clock frequency, that counts a preprogrammed numb |
| 5872967 |
Method for warm boot from reset |
February 16, 1999 |
| A computer system employs a process on warm boot which obviates the need to copy code in non-volatile memory to volatile memory; a normal function in a warm boot process. The computer system checks a warm boot flag which indicates that the code was previously copied on cold boot. By avoi |
| 5867655 |
Method to store privileged data within the primary CPU memory space |
February 2, 1999 |
| In the present invention, a single EEPROM is used to store firmware for the CPU, firmware for the SCP and the system password and other critical system data. Hardware protection is provided that prevents the CPU from accessing the portion of the EEPROM that contains the password or other |
| 5822601 |
Apparatus to allow a CPU to control the relocation of code blocks for other CPUs |
October 13, 1998 |
| The invention provides for a CPU in a digital system to control the location of the code being executed by one or more peripheral CPUs when all CPUs share a common memory. This allows the CPU to allocate convenient (e.g., unused) blocks of its address space for the code for the periphera |
| 5809290 |
Programmable hardware counter |
September 15, 1998 |
| A programmable hardware timer provides a relatively consistently measure of predetermined time intervals over a relatively wide range of performance levels. The programmable hardware timer includes a downcounter, driven by a predetermined clock frequency, that counts a preprogrammed numb |
| 5802376 |
Write once read only registers |
September 1, 1998 |
| The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are |
| 5784642 |
System for establishing a transfer mode between system controller and peripheral device |
July 21, 1998 |
| The present invention relates to a computer system and more particularly to a computer system which allows option controller cards for various input/output (I/O) devices to be added on the motherboard at minimum cost. |
| 5764995 |
Write once read only registers |
June 9, 1998 |
| The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are |
| 5752063 |
Write inhibited registers |
May 12, 1998 |
| The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are |
| 5748982 |
Apparatus for selecting a user programmable address for an I/O device |
May 5, 1998 |
| Manual insertion of hardware jumpers to configure I/O device selection and addressing is eliminated through the implementation of specialized hardware which allows for program control over several addressing paths. A register file is utilized within a programmable device to configure |
| 5748922 |
Method and apparatus for reading data from a write only port |
May 5, 1998 |
| The present invention relates to a method and apparatus to provide a write only register that is implemented with a low cost device yet provides the means whereby the register may be read, glitch free, using a predetermined procedure. |
| 5742841 |
Alternate I/O port access to standard register set |
April 21, 1998 |
| A method and apparatus providing alternate access to standard ports to enable the functionality of such standard ports to be expanded without the need to provide additional software or hardware while obviating the problem that any non-standard commands will be ignored. All standard c |
| 5687379 |
Method and apparatus for preventing unauthorized access to peripheral devices |
November 11, 1997 |
| This invention relates to a system for providing programmable configuration protection of a programmable Input/Output device. By configuration protection, it is meant that the programming options of an I/O controller can be set in accordance to a given environment, and then by use of a |
| 5596713 |
Method to prevent data loss in an electrically erasable read only memory |
January 21, 1997 |
| An apparatus and method for tracking and interception of instructions as they are presented to the memory, selectively passing harmless data to the device and disallowing the sequences which instruct the device to perform harmful functions, such as self-erase. A software trap is provided |
| 5574866 |
Method and apparatus for providing a data write signal with a programmable duration |
November 12, 1996 |
| A control circuit which allows computer systems to modify signal timing relationships in the hardware via programmable ports in the system, thereby allowing timing adjustments to be made without effecting motherboard hardware. The control circuit includes a plurality of delay devices |
| 5303352 |
Dual connector port for bus master card |
April 12, 1994 |
| A computer system includes a control circuit having a request input, and a pair of connectors which are electrically coupled to the control circuit and are each connected to the request input of the control circuit, each connector being capable of removably receiving a circuit card. The |
| 5291588 |
Control system and method for multiple rate disk drive data transfer with a single oscillator |
March 1, 1994 |
| A computer disk drive control adapts the rate of data transfer between a disk drive and a CPU to correspond to one of three industry standard transfer rates. The timing of disk controller signals is provided for by a two phase state machine that receives a signal representative of a |
| 5129069 |
Method and apparatus for automatic memory configuration by a computer |
July 7, 1992 |
| A memory system includes a memory unit with plural addressable storage locations, a connector arrangement for detachably electrically coupling the memory unit to a computer, and a decoding arrangement for determining whether a computer memory address is within a range of addresses to whi |
| 5072450 |
Method and apparatus for error detection and localization |
December 10, 1991 |
| A computer system reads data from selected locations in a memory while each address applied to the memory is temporarily stored in a register. If a data error is detected, two flipflops are set, one of which can generate and interrupt the central processing unit, and the other of which d |
