| Patent Number |
Title Of Patent |
Date Issued |
| 6888197 |
Power metal oxide semiconductor field effect transistor layout |
May 3, 2005 |
| A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions. Each of the cells is |
| 6821913 |
Method for forming dual oxide layers at bottom of trench |
November 23, 2004 |
| Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defin |
| 6784115 |
Method of simultaneously implementing differential gate oxide thickness using fluorine bearing i |
August 31, 2004 |
| Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (160) that is thin in some regions, such as the |
| 6660592 |
Fabricating a DMOS transistor |
December 9, 2003 |
| Embodiment of the present invention are directed to improving the performance of a DMOS transistor. A method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate, and implanting first conductive dopants into a surface |
| 6657263 |
MOS transistors having dual gates and self-aligned interconnect contact windows |
December 2, 2003 |
| A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconnect contact windows, and is c |
| 6284578 |
MOS transistors having dual gates and self-aligned interconnect contact windows |
September 4, 2001 |
| A method of fabricating an IC device on a substrate comprising MOS transistors and other IC components. Each of the transistors of the IC device comprises a raised source electrode, a raised drain electrode, dual gate electrodes and self-aligned interconnect contact windows, and is c |
| 6228729 |
MOS transistors having raised source and drain and interconnects |
May 8, 2001 |
| A process for fabricating a semiconductor device comprising a gate electrode, a raised source, a raised drain and an interconnect inlaid into an isolation region. A semiconductor device is fabricated by a process comprising the following steps: forming sequentially a first dielectric |
| 6150244 |
Method for fabricating MOS transistor having raised source and drain |
November 21, 2000 |
| A process for fabricating a semiconductor device comprising a raised source and drain. A semiconductor device is fabricated by a process comprising the following steps: forming active regions separated by isolation regions; forming at each active region a gate electrode structure; de |
| 6127699 |
Method for fabricating MOSFET having increased effective gate length |
October 3, 2000 |
| A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming |
| 6008106 |
Micro-trench oxidation by using rough oxide mask for field isolation |
December 28, 1999 |
| A method of forming isolation region of an integrated circuit by using rough oxide mask is described. First, a layer of first dielectric is formed on the surface of a silicon substrate. The first dielectric layer is then patterned to define active device region and isolation region. |
| 5972754 |
Method for fabricating MOSFET having increased effective gate length |
October 26, 1999 |
| A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming |
| 5804493 |
Method for preventing substrate damage during semiconductor fabrication |
September 8, 1998 |
| A method for preventing substrate damage during semiconductor fabrication, comprising, forming a pad oxide layer on the substrate, depositing a polysilicon buffer layer on the pad oxide layer, ion-implanting fluorine into the polysilicon buffer layer, depositing a silicon nitride layer o |
