| Patent Number |
Title Of Patent |
Date Issued |
| 7555738 |
Integrated structure layout and layout of interconnections for an instruction execution unit of |
June 30, 2009 |
| An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the r |
| 7555632 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
June 30, 2009 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 7555631 |
RISC microprocessor architecture implementing multiple typed register sets |
June 30, 2009 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 7487333 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
February 3, 2009 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 7343473 |
System and method for translating non-native instructions to native instructions for processing |
March 11, 2008 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a p |
| 7174525 |
Integrated structure layout and layout of interconnections for an instruction execution unit of |
February 6, 2007 |
| An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the r |
| 7162610 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
January 9, 2007 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 7051187 |
Superscalar RISC instruction scheduling |
May 23, 2006 |
| A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address |
| 7028161 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
April 11, 2006 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 6986024 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
January 10, 2006 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6965987 |
System and method for handling load and/or store operations in a superscalar microprocessor |
November 15, 2005 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load request |
| 6959375 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
October 25, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6954847 |
System and method for translating non-native instructions to native instructions for processing |
October 11, 2005 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 6954844 |
Microprocessor architecture capable of supporting multiple heterogeneous processors |
October 11, 2005 |
| A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of t |
| 6948052 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
September 20, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6941447 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
September 6, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6934829 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 23, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6915412 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
July 5, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6782521 |
Integrated structure layout and layout of interconnections for an instruction execution unit of |
August 24, 2004 |
| An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the r |
| 6647485 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
November 11, 2003 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6611908 |
Microprocessor architecture capable of supporting multiple heterogeneous processors |
August 26, 2003 |
| A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of t |
| 6425054 |
Multiprocessor operation in a multimedia signal processor |
July 23, 2002 |
| To achieve high performance at low cost, an integrated digital signal processor uses an architecture which includes both a general purpose processor and a vector processor. The integrated digital signal processor also includes a cache subsystem, a first bus and a second bus. The cache |
| 6405273 |
Data processing device with memory coupling unit |
June 11, 2002 |
| A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are prov |
| 6401232 |
Integrated structure layout and layout of interconnections for an instruction execution unit of |
June 4, 2002 |
| An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the r |
| 6401194 |
Execution unit for processing a data stream independently and in parallel |
June 4, 2002 |
| A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions |
| 6289433 |
Superscalar RISC instruction scheduling |
September 11, 2001 |
| A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address |
| 6282630 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
August 28, 2001 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 6272619 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 7, 2001 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6272579 |
Microprocessor architecture capable of supporting multiple heterogeneous processors |
August 7, 2001 |
| A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic |
| 6263423 |
System and method for translating non-native instructions to native instructions for processing |
July 17, 2001 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 6256720 |
High performance, superscalar-based computer system with out-of-order instruction execution |
July 3, 2001 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6249856 |
RISC microprocessor architecture implementing multiple typed register sets |
June 19, 2001 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 6219763 |
System and method for adjusting priorities associated with multiple devices seeking access to a |
April 17, 2001 |
| A system for transferring data in a microprocessor architecture including a memory array unit (MAU) and multiple devices seeking access to the MAU. The system has a row match circuit for detecting and indicating a row match between successive row addresses. The row match circuit include |
| 6173369 |
Computer system for processing multiple requests and out of order returns using a request queue |
January 9, 2001 |
| A system and method for processing a sequence of requests for data by one or more central processing units (CPUs) after cache misses. Each CPU request includes a CPU-ID tag identifying the CPU issuing the request for data and an address identifying a location in lower-level memory where |
| 6173349 |
Shared bus system with transaction and destination ID |
January 9, 2001 |
| To reduce latency on a shared bus during bus arbitration, a novel shared bus system uses device select lines between a bus arbiter and the bus devices to select the bus slave concurrently with the granting of the shared bus to the bus master. Specifically, a bus device requests the use |
| 6128723 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
October 3, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6101594 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 8, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6092181 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
July 18, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6083274 |
Integrated structure layout and layout of interconnections for an integrated circuit chip |
July 4, 2000 |
| An integrated structure layout of functional blocks and interconnections for an integrated execution unit of an integrated circuit chip. The functional blocks of the integrated execution unit include data dependency comparator logic, tag assignment logic, and register file port multiplex |
| 6058465 |
Single-instruction-multiple-data processing in a multimedia signal processor |
May 2, 2000 |
| A vector processor architecture provides vector registers of fixed size having data elements of programmable size and type. The type and size for data elements are defined by instructions which manipulate operands associated with the vector registers. The data size defined by an inst |
| 6044449 |
RISC microprocessor architecture implementing multiple typed register sets |
March 28, 2000 |
| A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set |
| 6038654 |
High performance, superscalar-based computer system with out-of-order instruction execution |
March 14, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6038653 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
March 14, 2000 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 5987593 |
System and method for handling load and/or store operations in a superscalar microprocessor |
November 16, 1999 |
| The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load request |
| 5983334 |
Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instruc |
November 9, 1999 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 5978838 |
Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor |
November 2, 1999 |
| An integrated multiprocessor architecture simplifies synchronization of multiple processing units. The multiple processing units constitute a general-purpose or control processor and a vector processor which has a single-instruction-multiple-data (SIMD) architecture so that multiple |
| 5974480 |
DMA controller which receives size data for each DMA channel |
October 26, 1999 |
| A DMA controller receives size data in association with a DMA request. If first size data is received, a first amount of data (for example, one word) is transferred through the DMA controller for the DMA request. If, on the other hand, second size data is received, then a second amount o |
| 5961629 |
High performance, superscalar-based computer system with out-of-order instruction execution |
October 5, 1999 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 5961628 |
Load and store unit for a vector processor |
October 5, 1999 |
| An apparatus coupled to a requesting unit and a memory. The apparatus includes a data path and a request control circuit. The data path is coupled to the requesting unit and the memory. The data path is for buffering a vector. The vector includes multiple data elements of a substanti |
| 5941979 |
Microprocessor architecture with a switch network and an arbitration unit for controlling access |
August 24, 1999 |
| A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O |
