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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Ngo; Minh Van
Address:
Union City, CA
No. of patents:
54
Patents:


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Patent Number Title Of Patent Date Issued
6903007 Process for forming bottom anti-reflection coating for semiconductor fabrication photolithograph June 7, 2005
An anti-reflective coating is formed between a material layer which is to be patterned on a semiconductor structure using photolithography, and an overlying photoresist layer. The anti-reflective coating suppresses reflections from the material layer surface into the photoresist layer
6713874 Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-la March 30, 2004
Degradation of organic-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ
6660634 Method of forming reliable capped copper interconnects December 9, 2003
The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper sil
6577009 Use of sic for preventing copper contamination of dielectric layer June 10, 2003
A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer
6576982 Use of sion for preventing copper contamination of dielectric layer June 10, 2003
A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer
6576545 Semiconductor devices with dual nature capping/ARC layers on fluorine doped silica glass inter-l June 10, 2003
Degradation of fluorine-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-sit
6566252 Method for simultaneous deposition and sputtering of TEOS and device thereby formed May 20, 2003
A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposi
6534869 Method for reducing stress-induced voids for 0.25 .mu.m micron and smaller semiconductor chip te March 18, 2003
A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms first, which subsequently volumetrically contracts, thereby
6492266 Method of forming reliable capped copper interconnects December 10, 2002
The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member: (a) under plasma conditions with ammonia and silane or dichlorosilane to form a copper sil
6399480 Methods and arrangements for insulating local interconnects for improved alignment tolerance and June 4, 2002
At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selective
6380588 Semiconductor device having uniform spacers April 30, 2002
A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
6333263 Method of reducing stress corrosion induced voiding of patterned metal layers December 25, 2001
Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a nitrogen-con
6323135 Method of forming reliable capped copper interconnects/with high etch selectivity to capping lay November 27, 2001
The selectivity of an etchant to a capping layer in a Cu or Cu alloy interconnect member is significantly enhanced by providing a dielectric layer thereon with a faster etch rate. Embodiments include forming the dielectric layer with a faster etch rate by PECVD: (a) at a low frequency
6303505 Copper interconnect with improved electromigration resistance October 16, 2001
Capping layer adhesion to a Cu or Cu alloy interconnect member is enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with a hydrogen plasma to substantially reduce oxides thereon, forming a thin layer of copper silicide on the treated surface and depositin
6251776 Plasma treatment to reduce stress corrosion induced voiding of patterned metal layers June 26, 2001
Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a plasma containin
6235632 Tungsten plug formation May 22, 2001
In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is formed on the first insulating layer and over an exposed surface of the metal line. An etc
6225210 High density capping layers with improved adhesion to copper interconnects May 1, 2001
The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by depositing the capping layer under high density plasma conditions at an elevated temperature, such as about 450.degree. C. to about 650.degree. C., e.g. about 450.degree. C. to
6221794 Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines April 24, 2001
In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases
6214731 Copper metalization with improved electromigration resistance April 10, 2001
Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a
6204136 Post-spacer etch surface treatment for improved silicide formation March 20, 2001
Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formatio
6190966 Process for fabricating semiconductor memory device with high data retention including silicon n February 20, 2001
A semiconductor memory device such as a flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes a floating gate with high data retention. A tungsten damascene local interconnect structure includes a silicon nitride etch stop layer which is formed using Plasma
6174743 Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines January 16, 2001
In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, a SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases
6171947 Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines January 9, 2001
In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, the substrate and interconnect lines are annealed prior to deposition of an ILD. A post annealing SiON layer is formed by using plasma-enhanced chemical vapor deposition.
6171919 MOS Transistor formation process including post-spacer etch surface treatment for improved silic January 9, 2001
Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formatio
6165894 Method of reliably capping copper interconnects December 26, 2000
The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with an ammonia plasma followed by depositing the diffusion barrier layer on the treated surfac
6153933 Elimination of residual materials in a multiple-layer interconnect structure November 28, 2000
A multiple-layer interconnect structure in an integrated circuit, is formed using damascene techniques. A first layer interconnect has a first dielectric layer through which at least one first layer conductor extends. A second layer interconnect is then formed on the first layer inte
6150285 Method for simultaneous deposition and sputtering of TEOS November 21, 2000
A method for making 0.25 micron semiconductor chips includes using TEOS as the high density plasma (HDP) inter-layer dielectric (ILD). More specifically, after establishing a predetermined aluminum line pattern on a substrate, TEOS is deposited and simultaneously with the TEOS deposi
6143672 Method of reducing metal voidings in 0.25 .mu.m AL interconnect November 7, 2000
In one embodiment, the present invention relates to a method of depositing a dielectric layer over a stacked interconnect structure, involving the steps of: providing a substrate having at least one stacked interconnect structure comprising at least one of an aluminum layer and an alumin
6140255 Method for depositing silicon nitride using low temperatures October 31, 2000
A method for depositing silicon nitride on a semiconductor wafer uses plasma enhanced chemical vapor deposition at very low temperatures. The temperature in a silicon nitride deposition chamber is set to be about 170.degree. C. or less. Silane gas (SiH.sub.4) flows into the silicon n
6127261 Method of fabricating an integrated circuit including a tri-layer pre-metal interlayer dielectri October 3, 2000
A method of depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cl
6121663 Local interconnects for improved alignment tolerance and size reduction September 19, 2000
At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively
6117799 Deposition of super thin PECVD SiO.sub.2 in multiple deposition station system September 12, 2000
The present invention provides a method and system for depositing an oxide layer onto a semiconductor device during fabrication by using a deposition chamber, the method comprising the steps of providing a temperature of less than approximately 450 degrees Celsius in the deposition chamb
6114235 Multipurpose cap layer dielectric September 5, 2000
A multipurpose cap layer serves as a bottom anti-reflective coating (BARC) during the formation of a resist mask, a hardmask during subsequent etching processes, a hardened surface during subsequent deposition and planarization processes, and optionally as a diffusion barrier to mobile
6114224 System and method for using N.sub.2 O plasma treatment to eliminate defects at an interface betw September 5, 2000
A system and method for using a nitrous oxide plasma treatment to eliminate defects at an interface between a stop layer and an integral layered dielectric. The system and method provide a reliable and simplified technology that eliminates the small bubble-like defects that can be co
6103611 Methods and arrangements for improved spacer formation within a semiconductor device August 15, 2000
Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently fo
6096662 NH.sub.3 /N.sub.2 plasma treatment to enhance the adhesion of silicon nitride to thermal oxide August 1, 2000
A method of manufacturing a semiconductor device with improved adhesion between the local interconnect etch stop layer and the thermal oxide in an isolation region. The thermal oxide is treated with an NH.sub.3 /N.sub.2 plasma. The local interconnect etch stop layer is either silicon nit
6096661 Method for depositing silicon dioxide using low temperatures August 1, 2000
A method for depositing silicon dioxide on a semiconductor wafer uses plasma enhanced chemical vapor deposition at very low temperatures. The temperature in a silicon dioxide deposition chamber is set to be about 170.degree. C. or less. Silane gas (SiH.sub.4) flows into the silicon d
6093973 Hard mask for metal patterning July 25, 2000
An oxide hard mask is formed between a deep ultraviolet photoresist and an anti-reflective coating to prevent interactions with the photoresist, thereby preventing reduction of a critical dimension of a patterned conductive layer. Embodiments include depositing a substantially nitrogen
6087275 Reduction of n-channel parasitic transistor leakage by using low power/low pressure phosphosilic July 11, 2000
A method of manufacturing a semiconductor device with increasing threshold voltage for parasitic transistor by forming a low power-low pressure phosphosilicate glass layer on the active regions and the field oxide regions.
6087271 Methods for removal of an anti-reflective coating following a resist protect etching process July 11, 2000
A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate following at least one etch back process associated with a spacer formation and/or subsequent resistor protect etching process or processes. The method eliminates the need to use HF acid in
6066567 Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etchi May 23, 2000
A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate during the etch back process associated with a resistor protect etch process. The method includes removing a silicon oxynitride BARC, in-situ, during a resistor protect etching process using
6060404 In-situ deposition of stop layer and dielectric layer during formation of local interconnects May 9, 2000
An in-situ deposition method allows for the forming of a dielectric layer suitable for use in forming a conductive path in a semiconductor wafer. The method includes depositing a thin SiO.sub.x N.sub.y stop layer on top of a semiconductor wafer within a chemical vapor deposition (CVD) re
6060393 Deposition control of stop layer and dielectric layer for use in the formation of local intercon May 9, 2000
A deposition method allows for the forming of a uniform dielectric stop layer that is substantially void of defects caused by outgassing effects. The stop layer is deposited in a reactor chamber at a higher than normal temperature of at least 480.degree. C. The stop layer is then combine
6054735 Very thin PECVD SiO.sub.2 in 0.5 micron and 0.35 micron technologies April 25, 2000
A very thin (less than 350 angstrom) layer of silicon dioxide (SiO.sub.2) is produced using plasma-enhanced chemical vapor deposition (PECVD) by substantially increasing the time duration of pre-coat and soak time steps of the PECVD process and substantially reducing the flow of silane
6051870 Process for fabricating semiconductor device including improved phosphorous-doped silicon dioxid April 18, 2000
A semiconductor structure includes a substrate, a microelectronic device formed on the substrate, and a dielectric layer including silicon dioxide formed over the microelectronic device. The silicon dioxide layer is doped with phosphorous in the form of approximately 96% SiO.sub.2 and 4%
6033584 Process for reducing copper oxide during integrated circuit fabrication March 7, 2000
A method of integrated circuit fabrication creating copper interconnect structures wherein the formation of copper oxide is reduced or eliminated by etching away the copper oxide performing an H.sub.2 plasma treatment in a plasma enhanced chemical vapor deposition chamber.
6027959 Methods for in-situ removal of an anti-reflective coating during a nitride resistor protect etch February 22, 2000
A method is provided for removing an bottom anti-reflective coating (BARC) from a transistor gate during an etch back process associated with a nitride resistor protect etch process. The method includes removing a silicon oxynitride BARC, in-situ, during an oxide resistor protect etching
6022799 Methods for making a semiconductor device with improved hot carrier lifetime February 8, 2000
A local interconnection to a device region in/on a substrate is formed by depositing either silicon oxynitride or silicon oxime as an etch stop layer, at a temperature of less than about 480.degree. C. to increase the hot carrier injection (HCI) lifetime of the resulting semiconductor
6020274 Method and system for using N.sub.2 plasma treatment to eliminate the outgassing defects at the February 1, 2000
The present invention provides a device and a method for substantially minimizing defects on the surface of the interface of the stop layer and the oxide layer during manufacturing of a semiconductor device. A method according to the present invention for minimizing defects in a semi
5990524 Silicon oxime spacer for preventing over-etching during local interconnect formation November 23, 1999
During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying
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