| Patent Number |
Title Of Patent |
Date Issued |
| 7534732 |
Semiconductor devices with copper interconnects and composite silicon nitride capping layers |
May 19, 2009 |
| Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having |
| 7482217 |
Forming metal-semiconductor films having different thicknesses within different regions of an el |
January 27, 2009 |
| A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second re |
| 7476604 |
Aggressive cleaning process for semiconductor device contact formation |
January 13, 2009 |
| A method of forming a contact through a material includes forming a via through a dielectric material and cleaning the via using a dilute hydrofluoric (DHF) acid solution. The method further includes depositing a barrier layer within the via and depositing metal adjacent the barrier |
| 7422961 |
Method of forming isolation regions for integrated circuits |
September 9, 2008 |
| A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low |
| 7341956 |
Disposable hard mask for forming bit lines |
March 11, 2008 |
| A method includes forming a group of disposable hard mask structures on a semiconductor device that includes a group of memory cells. The method further includes using the disposable hard mask structures to precisely control a junction profile of the memory cells. |
| 7323418 |
Etch-back process for capping a polymer memory device |
January 29, 2008 |
| The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides |
| 7312125 |
Fully depleted strained semiconductor on insulator transistor and method of making the same |
December 25, 2007 |
| An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide la |
| 7307322 |
Ultra-uniform silicide system in integrated circuit technology |
December 11, 2007 |
| A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed |
| 7307027 |
Void free interlayer dielectric |
December 11, 2007 |
| A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of t |
| 7300886 |
Interlayer dielectric for charge loss improvement |
November 27, 2007 |
| A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control |
| 7297592 |
Semiconductor memory with data retention liner |
November 20, 2007 |
| A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline |
| 7238571 |
Non-volatile memory device with increased reliability |
July 3, 2007 |
| A memory device may include a number of memory cells, a first interlayer dielectric formed over the memory cells and at least one metal layer formed over the interlayer dielectric. A dielectric layer may be formed over the metal layer. The dielectric layer may represent a cap layer f |
| 7217660 |
Method for manufacturing a semiconductor component that inhibits formation of wormholes |
May 15, 2007 |
| A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sac |
| 7157335 |
Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact r |
January 2, 2007 |
| The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of |
| 7151020 |
Conversion of transition metal to silicide through back end processing in integrated circuit tec |
December 19, 2006 |
| A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A transition metal layer is for |
| 7091088 |
UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory d |
August 15, 2006 |
| A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing over the charge trapping dielectric flash memory cell at least one UV-protective laye |
| 7074677 |
Memory with improved charge-trapping dielectric layer |
July 11, 2006 |
| A manufacturing method for a Flash memory includes depositing a first dielectric layer on a semiconductor substrate. A low hydrogen charge-trapping dielectric layer is deposited followed by a second dielectric layer. First and second bitlines are implanted and a wordline layer is dep |
| 7070911 |
Structure and method for reducing standing waves in a photoresist |
July 4, 2006 |
| A structure and method for reducing standing waves in a photoresist during manufacturing of a semiconductor is presented. Embodiments of the present invention include a method for reducing standing wave formation in a photoresist during manufacturing a semiconductor device comprising |
| 7064067 |
Reduction of lateral silicide growth in integrated circuit technology |
June 20, 2006 |
| A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconduct |
| 7060571 |
Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate diele |
June 13, 2006 |
| Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing |
| 7060554 |
PECVD silicon-rich oxide layer for reduced UV charging |
June 13, 2006 |
| A Si-rich silicon oxide layer having reduced UV transmission is deposited by PECVD, on an interlayer dielectric, prior to metallization, thereby reducing V.sub.t. Embodiments include depositing a UV opaque Si-rich silicon oxide layer having an R.I. of 1.7 to 2.0. |
| 7049666 |
Low power pre-silicide process in integrated circuit technology |
May 23, 2006 |
| A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin insulating layer is form |
| 7038320 |
Single damascene integration scheme for preventing copper contamination of dielectric layer |
May 2, 2006 |
| A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer |
| 7033888 |
Engineered metal gate electrode |
April 25, 2006 |
| A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such |
| 7023046 |
Undoped oxide liner/BPSG for improved data retention |
April 4, 2006 |
| Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 .AN |
| 7005376 |
Ultra-uniform silicides in integrated circuit technology |
February 28, 2006 |
| A method of forming and a structure of an integrated circuit are provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uni |
| 7005357 |
Low stress sidewall spacer in integrated circuit technology |
February 28, 2006 |
| A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed aro |
| 6989604 |
Conformal barrier liner in an integrated circuit interconnect |
January 24, 2006 |
| An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, process |
| 6989563 |
Flash memory cell with UV protective layer |
January 24, 2006 |
| A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric fl |
| 6979903 |
Integrated circuit with dielectric diffusion barrier layer formed between interconnects and inte |
December 27, 2005 |
| An integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier |
| 6972254 |
Manufacturing a conformal atomic liner layer in an integrated circuit interconnect |
December 6, 2005 |
| A manufacturing method for an integrated circuit has a substrate with a semiconductor device thereon. A channel dielectric layer is deposited over the device and has an opening provided therein. A reducing process is performed in order to reduce the oxidation on the conductor and a c |
| 6962857 |
Shallow trench isolation process using oxide deposition and anneal |
November 8, 2005 |
| A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in a strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which redu |
| 6955997 |
Laser thermal annealing method for forming semiconductor low-k dielectric layer |
October 18, 2005 |
| A method of manufacturing a semiconductor device, including depositing a first layer of dielectric material onto the device, laser thermal annealing a surface of the first layer, and depositing a second layer of dielectric material over the laser thermal annealed surface of the first |
| 6933219 |
Tightly spaced gate formation through damascene process |
August 23, 2005 |
| The invention includes an apparatus and a method of manufacturing such apparatus using a damascene process. The method includes the step of patterning a layer disposed over a substrate to include a line and space pattern. The line and space pattern in the layer includes at least one |
| 6905971 |
Treatment of dielectric material to enhance etch rate |
June 14, 2005 |
| In one embodiment, the present invention relates to a method for pre-treating and etching a dielectric layer in a semiconductor device comprising the steps of: (A) pre-treating one or more exposed portions of a dielectric layer with a plasma in a plasma etching tool to increase remov |
| 6900488 |
Multi-cell organic memory element and methods of operating and fabricating |
May 31, 2005 |
| The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of th |
| 6900121 |
Laser thermal annealing to eliminate oxide voiding |
May 31, 2005 |
| Oxide voiding is eliminated was substantially reduced by laser thermal annealing. Embodiments include fabricating flash memory devices by depositing a BPSG over spaced apart transistors as the first interlayer dielectric with voids formed in gaps between the transistors and laser the |
| 6897144 |
Cu capping layer deposition with improved integrated circuit reliability |
May 24, 2005 |
| The electromigration resistance of nitride capped Cu lines is significantly improved by controlling the nitride deposition conditions to reduce the compressive stress of the deposited nitride layer, thereby reducing diffusion along the Cu-nitride interface. Embodiments include depositing |
| 6893910 |
One step deposition method for high-k dielectric and metal gate electrode |
May 17, 2005 |
| A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed |
| 6884681 |
Method of manufacturing a semiconductor memory with deuterated materials |
April 26, 2005 |
| A method for manufacturing a MirrorBit.RTM. Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before comp |
| 6875694 |
Method of treating inlaid copper for improved capping layer adhesion without damaging porous low |
April 5, 2005 |
| An exposed surface of inlaid Cu is plasma treated for improved capping layer adhesion while controlling plasma conditions to avoid damaging porous low-k materials. Embodiments include forming a dual damascene opening in a porous dielectric material having a dielectric constant (k) of |
| 6861350 |
Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode |
March 1, 2005 |
| Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 .ANG. to 75 .ANG., and then introduc |
| 6849925 |
Preparation of composite high-K/standard-K dielectrics for semiconductor devices |
February 1, 2005 |
| A semiconductor device having a composite dielectric layer, including a semiconductor substrate, alternating sub-layers including a first dielectric material and a second dielectric material on the semiconductor substrate, the sub-layers forming a composite dielectric layer having at |
| 6836398 |
System and method of forming a passive layer by a CMP process |
December 28, 2004 |
| The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is p |
| 6836017 |
Protection of low-k ILD during damascene processing with thin liner |
December 28, 2004 |
| Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositin |
| 6835656 |
Method of forming ultra-shallow junctions in a semiconductor wafer with a deposited silicon laye |
December 28, 2004 |
| A method for forming ultra-shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high-resistivity metal |
| 6830998 |
Gate dielectric quality for replacement metal gate transistors |
December 14, 2004 |
| Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal d |
| 6828199 |
Monos device having buried metal silicide bit line |
December 7, 2004 |
| A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide |
| 6818557 |
Method of forming SiC capped copper interconnects with reduced hillock formation and improved el |
November 16, 2004 |
| The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH.sub.3 and N.sub.2, ramping up |
| 6809402 |
Reflowable-doped HDP film |
October 26, 2004 |
| Device leakage due to spacer undercutting is remedied by depositing a B-doped HDP or a BP-doped HDP oxide gap filling layer capable of flowing into undercut regions. Embodiments include depositing a B or BP-doped HDP oxide film containing 4 to 6 wt. % B over closely spaced apart non- |
