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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Ng; Hung Y.
Address:
New Milford, NJ
No. of patents:
9
Patents:












Patent Number Title Of Patent Date Issued
7785950 Dual stress memory technique method and related structure August 31, 2010
A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, anneali
7772676 Strained semiconductor device and method of making same August 10, 2010
A semiconductor body is formed from a first semiconductor material, e.g., silicon. A compound semiconductor region, e.g., silicon germanium, is embedded in the semiconductor body. The compound semiconductor region includes the first semiconductor material and a second semiconductor m
7452784 Formation of improved SOI substrates using bulk semiconductor wafers November 18, 2008
The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the s
7442619 Method of forming substantially L-shaped silicide contact for a semiconductor device October 28, 2008
A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, t
7307323 Structure to use an etch resistant liner on transistor gate structure to achieve high device per December 11, 2007
An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location
7064027 Method and structure to use an etch resistant liner on transistor gate structure to achieve high June 20, 2006
An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location
6884734 Vapor phase etch trim structure with top etch blocking layer April 26, 2005
A blocking layer is formed on a hard mask having an initial thickness. Lines are fabricated by patterning the blocking layer and the hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segme
6656375 Selective nitride: oxide anisotropic etch process December 2, 2003
An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH.sub.3 F or CH.sub.2 F.sub.2, the
6369434 Nitrogen co-implantation to form shallow junction-extensions of p-type metal oxide semiconductor April 9, 2002
A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to a predetermined depth preferably less than about 800 .ANG.. The gate electrode serves










 
 
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