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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
New; Daryl C.
Address:
Meridian, ID
No. of patents:
14
Patents:












Patent Number Title Of Patent Date Issued
7037848 Methods of etching insulative materials, of forming electrical devices, and of forming capacitor May 2, 2006
In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In
6753262 Methods of etching insulative materials, of forming electrical devices, and of forming capacitor June 22, 2004
In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In
6528429 Methods of etching insulative materials, of forming electrical devices, and of forming capacitor March 4, 2003
In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In
6358857 Methods of etching insulative materials, of forming electrical devices, and of forming capacitor March 19, 2002
In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are exposed to physical etching conditions within a reaction chamber and in the presence of at least one oxygen-containing gas. In
6331442 Pre-patterned contact fill capacitor for dielectric etch protection December 18, 2001
Disclosed is a capacitor incorporating a material having a high dielectric constant and a method of fabricating the same. In a preferred embodiment, the bottom electrode is first deposited and patterned. A thick, planarized insulating layer is deposited over the bottom electrode and a co
6297124 Method of improving alignment signal strength by reducing refraction index at interface of mater October 2, 2001
A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises
6133108 Dielectric etch protection using a pre-patterned via-fill capacitor October 17, 2000
Disclosed is a capacitor incorporating a material having a high dielectric constant and a method of fabricating the same. In a preferred embodiment, the bottom electrode is first deposited and patterned. An insulating diffusion barrier, such as LPCVD silicon nitride, is deposited over th
6096571 Method of improving alignment signal strength by reducing refraction index at interface of mater August 1, 2000
A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises
6060785 Method of improving alignment signal strength by reducing refraction index at interface of mater May 9, 2000
A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises
5985676 Method of forming capacitor while protecting dielectric from etchants November 16, 1999
Disclosed is a capacitor incorporating a material having a high dielectric constant and a method of fabricating the same. In a preferred embodiment, the bottom electrode is first deposited and patterned. A thick, planarized insulating layer is deposited over the bottom electrode and a co
5933743 Method of improving alignment signal strength by reducing refraction index at interface of mater August 3, 1999
A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises
5824590 Method for oxidation and crystallization of ferroelectric material October 20, 1998
A two-step method of low temperature oxidation of a ferroelectric layer followed by high temperature crystallization of the ferroelectric film to protect underlying semiconductor layers against high temperature oxidation which can cause the conductive layers thereof to become nonconducti
5801916 Pre-patterned contact fill capacitor for dielectric etch protection September 1, 1998
Disclosed is a capacitor incorporating a material having a high dielectric constant. In a preferred embodiment, the bottom electrode is first deposited and patterned. An insulating diffusion barrier, such as LPCVD silicon nitride, is deposited over the bottom electrode and a contact is
5631804 Contact fill capacitor having a sidewall that connects the upper and lower surfaces of the diele May 20, 1997
Disclosed is a capacitor incorporating a material having a high dielectric constant and a method of fabricating the same. In a preferred embodiment, the bottom electrode is first deposited and patterned. A thick, planarized insulating layer is deposited over the bottom electrode and a co










 
 
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