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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Nataraj; Bindiganavale S.
Address:
Cupertino, CA
No. of patents:
65
Patents:


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Patent Number Title Of Patent Date Issued
8089794 Precharge circuits and methods for content addressable memory (CAM) and related devices January 3, 2012
A method may include selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits; precharging the result line to the precharge potential by enabling a first precharge path while the compare data value
8031501 Segmented content addressable memory device having pipelined compare operations October 4, 2011
Present embodiments describe a CAM device having a segmented CAM array. Each segment of the CAM array, or cell blocks, includes one or more rows of CAM cells. One or more of the cell blocks in the CAM array are selectively enabled during a search operation based on a detected matchin
7943400 Integrated circuit device with electronically accessible device identifier May 17, 2011
An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to interrupt an otherwis
7920399 Low power content addressable memory device having selectable cascaded array segments April 5, 2011
A content addressable memory (CAM) device includes a CAM array and a configuration circuit. The CAM array has a plurality of rows of CAM cells, each row segmented into a plurality of row segments, each row segment including a plurality of CAM cells coupled to a corresponding match li
7920398 Adaptive match line charging April 5, 2011
A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and a pre-charge circuit. The detector circuit detects a voltage of the match line and generates a feedback
7920397 Memory device having bit line leakage compensation April 5, 2011
A memory device operates in a calibration mode during which the effects of bit line leakage current are measured and to operate in a normal mode during which the bit line current is adjusted to compensate for leakage according to the results of the calibration mode. In the calibration
7868383 Configurable non-volatile logic structure for characterizing an integrated circuit device January 11, 2011
An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells
7848129 Dynamically partitioned CAM array December 7, 2010
A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arrays. Each sub-array
7830691 Low power content addressable memory November 9, 2010
A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare l
7800930 Precharge circuits and methods for content addressable memory (CAM) and related devices September 21, 2010
An integrated circuit device can include a plurality of compare cell circuits that selectively provide charge transfer path between a result line and a reference node according to a comparison between a stored data value and an applied compare data value during a compare time period. A
7782084 Integrated circuit with reconfigurable inputs/outputs August 24, 2010
An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connect
7688609 Content addressable memory having dynamic match resolution March 30, 2010
A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in e
7589362 Configurable non-volatile logic structure for characterizing an integrated circuit device September 15, 2009
An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells
7505295 Content addressable memory with multi-row write function March 17, 2009
A content addressable memory (CAM) device having a multi-row write function. The CAM device includes a CAM array and an address circuit. The CAM array includes a plurality of CAM cells and word lines coupled to respective rows of the CAM cells. The address circuit is coupled to the C
7461295 Timing failure analysis in a semiconductor device having a pipelined architecture December 2, 2008
A method of testing a semiconductor device having a pipelined architecture. Operation of a first pipeline stage of the semiconductor is disabled during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device. A second pipe
7417881 Low power content addressable memory August 26, 2008
A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare l
7272027 Priority circuit for content addressable memory September 18, 2007
A digital signal processor having priority logic coupled to an array of storage elements, the priority logic to provide to a priority signal lines an indication of a location of a particular number in the array of storage elements. The priority logic includes compare circuits where each
7257763 Content addressable memory with error signaling August 14, 2007
A content addressable memory (CAM) device including a CAM array, encoding circuit, address circuit and error checking circuit. The encoding circuit generates an address value that corresponds to one of a plurality of match lines included within the CAM array. The address circuit receives
7246198 Content addressable memory with programmable word width and programmable priority July 17, 2007
A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The
7230841 Content addressable memory having dynamic match resolution June 12, 2007
A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in e
7215004 Integrated circuit device with electronically accessible device identifier May 8, 2007
An semiconductor device having a plurality of fabrication layers. A first region of a first fabrication layer of the semiconductor device is revised. To signal the revision, a connectivity structure in a second region of the first fabrication layer is omitted to interrupt an otherwis
7213101 Classless interdomain routing using binary content addressable memory having mask bits and mask May 1, 2007
A method and apparatus for using a binary CAM array to implement Classless Interdomain Routing (CIDR) Address processing. A binary CAM array is segmented into a plurality of array groups, each of which includes a number of rows of binary CAM cells, a group global mask circuit, and a
7171595 Content addressable memory match line detection January 30, 2007
According to one embodiment of the present invention, a content addressable memory (CAM) device includes a CAM array that includes a plurality of rows of CAM cells each coupled to a corresponding match line, and a test circuit coupled to the match lines that outputs row match results
7154764 Method of controlling a bit line for a content addressable memory December 26, 2006
A bit line control circuit is coupled between a bit line of an associated Content Addressable Memory (CAM) Array and a supply voltage. The bit line control circuit adjusts the charge current for the bit line in response to a bit line control signal. For some embodiments, the bit line con
7143231 Method and apparatus for performing packet classification for policy-based packet routing November 28, 2006
A method and apparatus for performing packet classification in a digital signal processor for policy-based packet routing. For one embodiment, the digital signal processor includes a policy statement table for storing policy statements. Each policy statement has associated with it a
7133302 Low power content addressable memory November 7, 2006
A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare l
7110408 Method and apparatus for selecting a most signficant priority number for a device using a partit September 19, 2006
A digital signal processor. The digital signal processor includes a content addressable memory (CAM) array for storing entries. The digital signal processor includes a partitioned priority index table having a plurality of rows and columns of priority blocks. Each row of the pluralit
7054993 Ternary content addressable memory device May 30, 2006
A ternary content addressable memory device. The device includes a ternary CAM array segmented into a plurality of array groups, each of which includes a number of rows of ternary CAM cells. Each array group is assigned to a particular priority by storing the priority number for each
7019999 Content addressable memory with latching sense amplifier March 28, 2006
A content addressable memory (CAM) device including a plurality of CAM cells, a pair of bit lines and a sense amplifier. Each of the plurality of CAM cells includes a static storage circuit to store a data value and is coupled to the pair of bit lines. The sense amplifier includes a firs
7016243 Content addressable memory having column redundancy March 21, 2006
A content addressable memory (CAM) having a main array including a plurality of columns of CAM cells, a spare column of CAM cells selectable to functionally replace a defective column of CAM cells in the main array, and circuitry to shift data corresponding to the defective column an
6961810 Synchronous content addressable memory November 1, 2005
A CAM device to perform in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction; (3) perform the comparison of the comparand data with a first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matchin
6944709 Content addressable memory with block-programmable mask write mode, word width and priority September 13, 2005
A content addressable memory (CAM) device comprising a plurality of CAM blocks and a block control circuit. The plurality of CAM blocks each includes an array of CAM cells to store data words and an array of priority number storage circuits to store priority numbers. Each priority nu
6944039 Content addressable memory with mode-selectable match detect timing September 13, 2005
A content addressable memory (CAM) device with mode-selectable match detect timing. The CAM device includes a plurality of rows of CAM cells coupled to respective match lines. Storage circuits are coupled to the match lines and configured to store match indications signaled thereon in re
6934795 Content addressable memory with programmable word width and programmable priority August 23, 2005
A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The
6910097 Classless interdomain routing using binary content addressable memory June 21, 2005
A method and apparatus for using a binary CAM array to implement Classless Interdomain Routing (CIDR) address processing. A binary CAM array is segmented into a plurality of array groups, each of which includes a number of rows of binary CAM cells and an associated group global mask.
6906937 Bit line control circuit for a content addressable memory June 14, 2005
A bit line control circuit is coupled between a bit line of an associated Content Addressable Memory (CAM). Array and a supply voltage. The bit line control circuit adjusts the charge current for the bit line in response to a bit line control signal. For some embodiments, the bit line co
6898099 Content addressable memory having dynamic match resolution May 24, 2005
A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in e
6845025 Word line driver circuit for a content addressable memory January 18, 2005
A word line driver circuit is coupled to a word line of an associated Content Addressable Memory (CAM) array. The word line driver circuit adjusts the word line read voltage in response to a compare signal indicative of whether the CAM array is performing a concurrent compare operati
6804135 Content addressable memory having column redundancy October 12, 2004
A content addressable memory (CAM) having a main array including a plurality of columns of CAM cells, a spare column of CAM cells selectable to functionally replace a defective column of CAM cells in the main array, and circuitry to shift data corresponding to the defective column and da
6757779 Content addressable memory with selectable mask write mode June 29, 2004
A content addressable memory (CAM) that includes a CAM array and a write circuit. The write circuit is coupled the CAM array and has a coding circuit to convert a first value into a second value, and a select circuit to select either the first value or the second value to be stored in th
6714430 Content addressable memory having column redundancy March 30, 2004
A content addressable memory (CAM) having a main array including a plurality of columns of CAM cells, a spare column of CAM cells selectable to functionally replace a defective column of CAM cells in the main array, a steering circuit for steering data corresponding to the defective colu
6697911 Synchronous content addressable memory February 24, 2004
A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to com
6678786 Timing execution of compare instructions in a synchronous content addressable memory January 13, 2004
A content address memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare
6574702 Method and apparatus for determining an exact match in a content addressable memory device June 3, 2003
A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the corresponding CAM cells, and a mask override circuit. Each local mask cell includes a ma
6567340 Memory storage cell based array of counters May 20, 2003
A multi-counter based system having a counter array. Each counter of the array having a memory cell. The system also includes an address decoder coupled to the counter array to select at least one of the memory cells within the counter array and read/write circuitry coupled to the counte
6564289 Method and apparatus for performing a read next highest priority match instruction in a content May 13, 2003
A content address memory (CAM) device that implements a read text highest priority or "RNHPM" instruction. The CAM device initially searches its CAM locations for a match with comparand data. If multiple matches are identified, then the CAM device initially outputs the highest priority
6539455 Method and apparatus for determining an exact match in a ternary content addressable memory devi March 25, 2003
A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the corresponding CAM cells, and a mask override circuit. Each local mask cell includes a ma
6499081 Method and apparatus for determining a longest prefix match in a segmented content addressable m December 24, 2002
A method and apparatus for determining a longest prefix match in a segmented content addressable memory (CAM) device. The CAM device includes multiple CAM array blocks that each may be arbitrarily loaded with CIDR addresses. For one embodiment, each CAM array is a ternary CAM array that
6445628 Row redundancy in a content addressable memory September 3, 2002
A CAM device that allows defective rows in one CAM block to be functionally replaced by spare rows from any CAM block in the device. In some embodiments, the CAM device includes a main address decoder, a plurality of CAM blocks, a corresponding plurality of spare address decoders, and a
6418042 Ternary content addressable memory with compare operand selected according to mask value July 9, 2002
A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to com
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