| Patent Number |
Title Of Patent |
Date Issued |
| 7388277 |
Chip and wafer integration process using vertical connections |
June 17, 2008 |
| A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate i |
| 7115997 |
Seedless wirebond pad plating |
October 3, 2006 |
| An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer. |
| 7084479 |
Line level air gaps |
August 1, 2006 |
| In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion |
| 7064064 |
Copper recess process with application to selective capping and electroless plating |
June 20, 2006 |
| An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only |
| 7030481 |
High density chip carrier with integrated passive devices |
April 18, 2006 |
| A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the support |
| 6975032 |
Copper recess process with application to selective capping and electroless plating |
December 13, 2005 |
| An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only abo |
| 6962872 |
High density chip carrier with integrated passive devices |
November 8, 2005 |
| A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the support |
| 6927472 |
Fuse structure and method to form the same |
August 9, 2005 |
| A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned e |
| 6924185 |
Fuse structure and method to form the same |
August 2, 2005 |
| A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned e |
| 6856025 |
Chip and wafer integration process using vertical connections |
February 15, 2005 |
| A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate i |
| 6831363 |
Structure and method for reducing thermo-mechanical stress in stacked vias |
December 14, 2004 |
| An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower met |
| 6700161 |
Variable resistor structure and method for forming and programming a variable resistor for elect |
March 2, 2004 |
| A non-ablative structure and method for forming a variable resistor includes providing a programmable resistive element including two or more different conductive materials, and changing a resistance of the programmable resistive element to a finite value by heating the programmable |
| 6697037 |
TFT LCD active data line repair |
February 24, 2004 |
| A matrix addressed display system designed so as to enable data line repair by electronic mechanisms which is efficient and low in cost and thus increases yield. Such active data line repair utilizes additional data driver outputs, a defect map memory in the TFT/LCD module and modificati |
| 6624499 |
System for programming fuse structure by electromigration of silicide enhanced by creating tempe |
September 23, 2003 |
| The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potentia |
| 6599778 |
Chip and wafer integration process using vertical connections |
July 29, 2003 |
| A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate i |
| 6566238 |
Metal wire fuse structure with cavity |
May 20, 2003 |
| An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above |
| 6495901 |
Multi-level fuse structure |
December 17, 2002 |
| A semiconductor device has a first conductor and a second conductor for fuse terminals. A fuse portion is disposed on a different level relative to both the first conductor and the second conductor. A first contact connects the fuse portion to the first conductor, and a second contact |
| 6486526 |
Crack stop between neighboring fuses for protection from fuse blow damage |
November 26, 2002 |
| A fuse structure in an integrated circuit chip is described that includes an insulated semiconductor substrate; a fuse bank integral to the insulated semiconductor substrate consisting of a plurality of parallel co-planar fuse links; and voids interspersed between each pair of the fuse |
| 6436585 |
Method of using optical proximity effects to create electrically blown fuses with sub-critical d |
August 20, 2002 |
| A method of making a photolithography mask for use in creating an electrical fuse on a semiconductor structure comprises initially determining a pattern for a desired electrical fuse, with the pattern including a fuse portion of substantially constant width except for a localized nar |
| 6420216 |
Fuse processing using dielectric planarization pillars |
July 16, 2002 |
| An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a |
| 6380003 |
Damascene anti-fuse with slot via |
April 30, 2002 |
| Interconnect structures comprising a substrate having a first level of electrically conductive features formed thereon; a patterned interlevel dielectric material formed on said substrate, wherein said patterned interlevel dielectric includes via spaces, wherein at least one of said |
| 6323535 |
Electrical fuses employing reverse biasing to enhance programming |
November 27, 2001 |
| A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and inc |
| 6301903 |
Apparatus for activating fusible links on a circuit substrate |
October 16, 2001 |
| A method and apparatus for activating fusible links on a circuit substrate. The circuit substrate is supported in a fixture which is cooled to a below ambient temperature. Cooling of the circuit substrate decreases the absorption of energy by the substrate, permitting a smaller spot size |
| 6295128 |
Optical alignment of superpositioned objects |
September 25, 2001 |
| In alignment of superpositioned objects on opposing substrates accuracy and simplicity is achieved through relative movement of the substrates responsive to an image of one object reflected from the surface of the opposite substrate. Alignment of mating fine pitch conductors and pads for |
| 6288436 |
Mixed fuse technologies |
September 11, 2001 |
| A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, |
| 6274440 |
Manufacturing of cavity fuses on gate conductor level |
August 14, 2001 |
| A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electri |
| 6268638 |
Metal wire fuse structure with cavity |
July 31, 2001 |
| An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above |
| 6266272 |
Partially non-volatile dynamic random access memory formed by a plurality of single transistor c |
July 24, 2001 |
| A Partially Non-Volatile Dynamic Random Access Memory (PNDRAM) uses a DRAM array formed by a plurality of single transistor (1T) cells or two transistor (2T) cells. The cells are electrically programmable as a non-volatile memory. This results in a single chip design featuring both, |
| 6242789 |
Vertical fuse and method of fabrication |
June 5, 2001 |
| A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and |
| 6218279 |
Vertical fuse and method of fabrication |
April 17, 2001 |
| A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and |
| 6208008 |
Integrated circuits having reduced stress in metallization |
March 27, 2001 |
| The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the |
| 6141267 |
Defect management engine for semiconductor memories and memory systems |
October 31, 2000 |
| A defect management engine (DME) for memories integrates a plurality of redundancy data cells and a plurality of redundancy address cells in the same array. The redundancy data cells are used for replacing defective cells in the memories. The redundancy address cells store the addresses |
| 6127721 |
Soft passivation layer in semiconductor fabrication |
October 3, 2000 |
| The use of an etch stop layer to define a terminal via opening to access a device feature after formation of a photosensitive soft-passivation layer. The etch stop layer allows the size of the terminal via opening to be decoupled from the resolution capabilities of current photosensitive |
| 6081021 |
Conductor-insulator-conductor structure |
June 27, 2000 |
| An integrated circuit device including a conductor-insulator-conductor structure and a method of manufacturing the structure simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings extend through a second interl |
| 6063651 |
Method for activating fusible links on a circuit substrate |
May 16, 2000 |
| A method and apparatus for activating fusible links on a circuit substrate. The circuit substrate is supported in a fixture which is cooled to a below ambient temperature. Cooling of the circuit substrate decreases the absorption of energy by the substrate, permitting a smaller spot size |
| 6037648 |
Semiconductor structure including a conductive fuse and process for fabrication thereof |
March 14, 2000 |
| A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fab |
| 6029881 |
Micro-scale part positioning by surface interlocking |
February 29, 2000 |
| A principle of surface interlocking wherein the imperfections of two parallel surfaces deform and interlock under pressure. The surface interlocking enables the combination of a bridging element and a bonding tip of a diffusion bonding apparatus to pick up, transport, position at a u |
| 6008523 |
Electrical fuses with tight pitches and method of fabrication in semiconductors |
December 28, 1999 |
| A semiconductor device includes an array of electrical fuses having a structure which permits tight fuse pitches while enabling electrical fusing at voltages of about 10 volts or less. The fuses are useful to replace defective components of the device and/or to permit custom wiring. |
| 5948286 |
Diffusion bonding of lead interconnections using precise laser-thermosonic energy |
September 7, 1999 |
| Thin film diffusion bonding of lead assemblies under severly limited spacing, thermal and pressure conditions is achieved through application of precisely controlled energy at the bond interface. The precisely controlled energy is a laser thermosonic energy pulse, delivered through a |
| 5939335 |
Method for reducing stress in the metallization of an integrated circuit |
August 17, 1999 |
| The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the |
| 5818563 |
Substrate structure and assembly method for reduced spatial light modulator size |
October 6, 1998 |
| A spatial light modulator designed to use a minimum area on the surface of a silicon substrate. This invention comprises a silicon substrate on a back plate with a glass cover that is used to seal liquid crystal between the glass cover and the silicon substrate. Most importantly, the glu |
| 5764314 |
Mechanical packaging and thermal management of flat mirror arrays |
June 9, 1998 |
| A liquid crystal element, a packaging structure providing thermal and alignment control, a display device including the same, and methods of fabrication and assembly are provided. The liquid crystal element includes: a semiconductor wafer, having microcircuitry and an array of reflec |
| 5721602 |
Mechanical packaging and thermal management of flat mirror arrays |
February 24, 1998 |
| A liquid crystal element, a packaging structure providing thermal and alignment control, a display device including the same, and methods of fabrication and assembly are provided. The liquid crystal element includes: a semiconductor wafer, having microcircuitry and an array of reflec |
| 5687078 |
Fine pitch bonding |
November 11, 1997 |
| In a bonding station, a tooling principle is provided wherein first and second tool parts respectively hold first and second apparatus parts, each apparatus part having fine conductor periodicity edge bonding regions, in superpositioned registration with the tool parts providing space an |
| 5659153 |
Thermoformed three dimensional wiring module |
August 19, 1997 |
| The present invention provides a wiring module containing a plurality of laminated polymer layers containing defined electronic circuitry which can be thermoformed into desired three dimensional shapes without damaging the internal wiring at the region of thermoform stress. More particul |
| 5641114 |
Controlled temperature bonding |
June 24, 1997 |
| In a bonding station the parts of the apparatus to be bonded are retained at a thermal bias temperature at a permitted level and a thermal check valve interface is provided between the bonding location and the part of the station that would serve as a conduction heat sink, thereby therma |
| 5619357 |
Flat panel display containing black matrix polymer |
April 8, 1997 |
| A thin film transistor display that comprises a black matrix polymer layer, comprising a polymer having an optical density of at least about 0.8 per .mu.m and being self-absorbent of visible light and being selected from the group consisting of substituted and unsubstituted polyanilines, |
| 5569950 |
Device to monitor and control the temperature of electronic chips to enhance reliability |
October 29, 1996 |
| Device to monitor and control the temperature of electronic chips to enhance reliability including a thermal electric cooling device in which the cold side is thermally secured to the chip and the hot side is attached to a heat sink. A thermocouple is sandwiched between the TEC devic |
| 5534094 |
Method for fabricating multi-layer thin film structure having a separation layer |
July 9, 1996 |
| A method and apparatus for releasing a workpiece from a substrate including providing a substrate which is transparent to a predetermined wavelength of electromagnetic radiation; forming, on the substrate, a separation layer which degrades in response to the predetermined radiation; prov |
| 5471090 |
Electronic structures having a joining geometry providing reduced capacitive loading |
November 28, 1995 |
| Electrical interconnection structures are described. The electrical interconnection structures are formed by electrically interconnecting in a stack a plurality of discrete substrates. By using a plurality of discrete substrates, a multilayer dielectric/electrical conductor structure can |
