| Patent Number |
Title Of Patent |
Date Issued |
| 7573772 |
Semiconductor memory device and self-refresh method therefor |
August 11, 2009 |
| A semiconductor memory device and a self-refresh method in which the semiconductor memory device includes a plurality of input/output ports having respective independent operation, a period of self-refresh through one of the plurality of input/output ports being subordinate to a kind of |
| 7555625 |
Multi-memory chip and data transfer method capable of directly transferring data between interna |
June 30, 2009 |
| A multi-memory chip and data transfer method are capable of directly transferring data between internal memory devices. The multi-memory chip of the present invention includes a first memory device, a second memory device, and a data transmission bus that is shared by the memory devices. |
| 7440352 |
Semiconductor memory device capable of selectively refreshing word lines |
October 21, 2008 |
| A semiconductor memory device comprises a plurality of memory cells connected to a plurality of word lines grouped in word line sets. Each of the word line sets is connected to a word line enable signal generation unit which stores information indicating whether data has been written to |
| 7385859 |
Semiconductor memory devices and methods for generating column enable signals thereof |
June 10, 2008 |
| A semiconductor memory device includes a column enable signal generator, a row enable signal generator and a final column enable signal generator. The column signal enable generator may generate a latency control signal and generating a buffered clock signal as a column enable signal in |
| 7095670 |
Semiconductor memory having variable memory size and method for refreshing the same |
August 22, 2006 |
| A semiconductor memory device is operable in a full capacity mode and at least one reduced capacity mode, and includes a memory array having a plurality of memory blocks, each of the memory blocks having at least one word line. An address generation circuit generates a first multi-bit |
| 7068559 |
Word line enable timing determination circuit of a memory device and methods of determining word |
June 27, 2006 |
| A word line enable timing determination circuit of a memory device and method of determining word line enable timing in a memory device may be configured to adjust enable timing at which to activate a word line for at least one read/write command input to the memory device. This may be |
| 6928016 |
Refresh type semiconductor memory device having refresh circuit for minimizing refresh fail at h |
August 9, 2005 |
| In the refresh type semiconductor memory device having a plurality of refresh type memory cells, for internally performing a refresh operation without an external command together with an input and output operation of data; the refresh type semiconductor memory device includes a refresh |
| 6847572 |
Refresh control circuit and methods of operation and control of the refresh control circuit |
January 25, 2005 |
| A refresh operation in a PSRAM device to hidden-refresh an internal memory cell by using a refresh pulse signal may be controlled by forming a dummy duration for the refresh operation in a read/write cycle, reducing the dummy duration when the refresh pulse signal is not generated, and |
| 6633995 |
System for generating N pipeline control signals by delaying at least one control signal corresp |
October 14, 2003 |
| A high-speed pipeline device includes n data path circuits connected in cascade between an input terminal and an output terminal. N data passing circuits have transmission times {T1, . . . , Tn} each less than a period P of a reference clock signal, at least one of the transmission times |
| 6542425 |
Refresh control circuit for controlling refresh cycles according to values stored in a register |
April 1, 2003 |
| A refresh control circuit is provided for controlling refresh cycles according to values stored in a register. A related refreshing method is also provided. The refresh control circuit controls the refresh cycles so as to refresh data stored in memory cells. The refresh control circuit |
| 6108244 |
Synchronous memory devices having dual port capability for graphics and other applications |
August 22, 2000 |
| Graphics memory devices include an output register having an input electrically coupled to an output signal line (DO) and first and second data output buffers responsive to first and second clock signals (CLK1, CLK2), respectively. The first data output buffer has an input electrical |
