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Inventor:
Nakatsuka; Yasuhiro
Address:
Hitachi, JP
No. of patents:
16
Patents:












Patent Number Title Of Patent Date Issued
7111187 Information processor and information processing system utilizing interface for synchronizing cl September 19, 2006
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit
6675311 Data processing system generating clock signal from an input clock, phase locked to the input cl January 6, 2004
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit
5974560 Information processor and information processing system utilizing clock signal October 26, 1999
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit
5968160 Method and apparatus for processing data in multiple modes in accordance with parallelism of pro October 19, 1999
A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the
5784630 Method and apparatus for processing data in multiple modes in accordance with parallelism of pro July 21, 1998
A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the
5680637 Computer having a parallel operating capability October 21, 1997
A RISC processor is arranged to reduce a code size, make the hardware less complicated, execute a plurality of operations for one machine cycle, and enhance the performance. The processor is capable of executing N instruction each having a short word length for indicating a single op
5640547 Data processing system generating clock signal from an input clock, phase locked to the input cl June 17, 1997
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit
5561775 Parallel processing apparatus and method capable of processing plural instructions in parallel o October 1, 1996
A parallel processing apparatus which includes a program counter for indicating instructions to be read out from a memory, an instruction register for storing a plurality of consecutive instructions read out from an address of the memory indicated by the program counter, a plurality of
5542083 Information processor and information processing system utilizing clock signal July 30, 1996
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit
5506982 Data processing system generating clock signal from an input clock, phase locked to the input cl April 9, 1996
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit
5404472 Parallel processing apparatus and method capable of switching parallel and successive processing April 4, 1995
When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing paral
5388249 Data processing system generating clock signal from an input clock, phase locked to the input cl February 7, 1995
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit
5287465 Parallel processing apparatus and method capable of switching parallel and successive processing February 15, 1994
When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing paral
5274829 Information processing apparatus having micro instructions stored both in on-chip ROM and off-ch December 28, 1993
A data processing apparatus which allows a large number of micro instructions to be read at high speeds by storing frequently used micro instructions in the on-chip ROM and those less frequently used in the off-chip memory. From the address of the micro instruction to be accessed, it
5133064 Data processing system generating clock signal from an input clock, phase locked to the input cl July 21, 1992
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit
4975839 Instruction decode method and arrangement suitable for a decoder of microprocessors December 4, 1990
An instruction decode method and arrangement suitable for a high-speed microprocessor are disclosed. The instruction decode arrangement comprises a high-speed PLA decoder of small capacity for decoding an instruction word having a small execution cycle, a low-speed PLA decoder of large










 
 
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