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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Mueller; Gerhard
Address:
Wappingers Falls, NY
No. of patents:
29
Patents:












Patent Number Title Of Patent Date Issued
6668031 Synchronized data capturing circuits using reduced voltage levels and methods therefor December 23, 2003
A synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized data circuit employs voltage signals having a reduced voltage level, the data signal and the timing signal having a first volta
6593613 Memory cell for plateline sensing July 15, 2003
Sensing of information from a memory cell via a plateline is disclosed. The memory cell comprises a bitline coupled to a junction of a cell transistor while the other junction is coupled to an electrode of the capacitor. The bitline is coupled to a constant voltage source. A plateline is
6529054 Prefetch architectures for data and time signals in an integrated circuit and methods therefor March 4, 2003
A synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to output a synchronized data capture signal. The synchronized data capture circuit includes a timer generator having a first time
6522171 Method of reducing sub-threshold leakage in circuits during standby mode February 18, 2003
A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after
6420908 Sense amplifier July 16, 2002
Providing an active signal that increases the gate overdrive voltage of the driver of a sense amplifier enables the use of smaller drivers. This facilitates more efficient layouts and/or smaller sense amplifiers, thereby reducing the chip size.
6370055 Semiconductor memory having asymmetric column addressing and twisted read write drive (RWD) line April 9, 2002
There is provided a semiconductor memory having a plurality of memory units. The memory includes a plurality of read write drive (RWD) lines horizontally and/or vertically twisted such that the RWD lines are shared between the plurality of memory units. A plurality of columns is included
6359471 Mixed swing voltage repeaters for high resistance or high capacitance signal lines and methods t March 19, 2002
A mixed swing voltage repeater circuit operates with reduced voltage signals, that is signals having a voltage level that is below a full swing voltage level. The mixed swing voltage repeater circuit is configured to be coupled to the signal line and has an input node coupled to a first
6335652 Method and apparatus for the replacement of non-operational metal lines in DRAMS January 1, 2002
A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit blo
6327170 Reducing impact of coupling noise in multi-level bitline architecture December 4, 2001
An integrated circuit comprising first and second bitline pairs 410 and 420 is described. The bitline paths of a bitline pair are on different bitline levels. The bitline paths of the first and second bitline pairs which are on different bitline levels are adjacent to each other. The fir
6320780 Reduced impact from coupling noise in diagonal bitline architectures November 20, 2001
An integrated circuit comprising first and second adjacent signal line pairs 310 and 320 is described. The signal line pairs comprise diagonal signal paths 311p, 312p; 321p and 322p with directional changes 335. The first signal line pair comprises m twists 340, where m is a whole number
6313663 Full swing voltage input/full swing output bi-directional repeaters for high resistance or high November 6, 2001
A bidirectional full swing voltage repeater implemented on a signal line of an integrated circuit, which includes a first enable node for providing a first enable signal and a second enable node for providing a second enable signal. There is included a first full-swing unidirectional rep
6307397 Reduced voltage input/reduced voltage output repeaters for high capacitance signal lines and met October 23, 2001
A method in an integrated circuit for implementing a reduced voltage repeater circuit on a signal line having thereon reduced voltage signals. The reduced voltage signals has a voltage level that is below V.sub.DD. The reduced voltage repeater circuit is configured to be coupled to the
6291335 Locally folded split level bitline wiring September 18, 2001
A method for fabricating a semiconductor memory with a split level folded bitline structure consisting of three contact levels, in accordance with the present invention includes forming gate structures for transistors in an array region and a support region of a substrate. First contacts
6272062 Semiconductor memory with programmable bitline multiplexers August 7, 2001
There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups; at least one sense amplifier; a first and a second multiplexer; and at least one programmable control device. Each multiplexer is adapted to couple at least one of
6259309 Method and apparatus for the replacement of non-operational metal lines in DRAMS July 10, 2001
A semiconductor integrated circuit device including a redundant metal line for replacing a non-operational metal line for connecting to a circuit block. The invention further includes a method for decoupling a defective or otherwise non-operational conductive data line from a circuit blo
6215349 Capacitive coupled driver circuit April 10, 2001
A high performance driver circuit is described. The driver produces increased current flow at its output to decrease charging time. Increased current flow is achieved by providing an overdrive circuit that provides a voltage offset to increase the magnitude of the overdrive voltage.
6201730 Sensing of memory cell via a plateline March 13, 2001
Sensing of information from a memory cell via a plateline is disclosed. The memory cell comprises a bitline coupled to a junction of a cell transistor while the other junction is coupled to an electrode of the capacitor. The bitline is coupled to a constant voltage source. A plateline is
6194953 Circuit configuration for generating an internal supply voltage February 27, 2001
A circuit configuration generates an internal supply voltage for integrated circuits at two different levels, each of which are constant. The selection of the levels is made solely on the basis of the magnitude of an external supply voltage. As a result, it is possible to switch back and
6188598 Reducing impact of coupling noise February 13, 2001
An integrated circuit comprising a first bitline pair 310 on a first bitline level which is adjacent to a second bitline pair 320 on a second bitline level is provided. The first bitline pair comprises m twists 340, where m is a whole number.gtoreq.1 and the second bitline pair comprises
6181165 Reduced voltage input/reduced voltage output tri-state buffers January 30, 2001
There is disclosed a tri-state buffer circuit for receiving an input signal at a buffer input node and transmitting, responsive to a buffer enable signal, an output signal at a buffer output node. The buffer circuit includes an input stage coupled to the buffer input node. The input stag
6140855 Dynamic-latch-receiver with self-reset pointer October 31, 2000
A dynamic latch receiver device comprises a sequence of data latch devices arranged in parallel for enabling sequential latching of data signals communicated serially on a single data line. The device includes a first pointer signal generator for generating a sequence of one or more firs
6127878 Driver circuit with negative lower power rail October 3, 2000
A high frequency driver circuit is described. The driver produces increased current flow at its output to decrease charging time, thereby enabling higher frequency operations. Increased current flow is achieved by providing an active control signal that increases the magnitude of the
6081479 Hierarchical prefetch for semiconductor memories June 27, 2000
A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least
6069815 Semiconductor memory having hierarchical bit line and/or word line architecture May 30, 2000
Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including firs
5923605 Space-efficient semiconductor memory having hierarchical column select line architecture July 13, 1999
Disclosed is a multiple bank semiconductor memory (40) (e.g., DRAM) capable of overlapping write/read operation to/from memory cells of different banks (MAa, MAb), and having a space efficient layout. Chip size is kept small by employing a single column decoder (44) for different banks,
5917744 Semiconductor memory having hierarchical bit line architecture with interleaved master bitlines June 29, 1999
Disclosed is a semiconductor memory employing a hierarchical bitline architecture which allows for a widened master bitline pitch as well as low bitline capacitance. In an exemplary embodiment, the memory (30) includes a plurality of memory cells (MC) arranged in rows and columns for
5909388 Dynamic random access memory circuit and methods therefor June 1, 1999
A memory circuit having a stitched architecture wherein word lines of the memory circuit comprise a low resistance conductor stitched to a gate conductor portion having a higher resistance than the low resistance conductor. The memory circuit includes an array of memory cells having
5877994 Space-efficient MDQ switch placement March 2, 1999
A semiconductor memory having a plurality of memory cells arranged in rows and columns includes a bank of sense amplifiers disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier in the bank disposed in a sense amplifier region
5831912 Semiconductor memory having space-efficient layout November 3, 1998
The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally










 
 
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