| Patent Number |
Title Of Patent |
Date Issued |
| 7627795 |
Pipelined data processor with deterministic signature generation |
December 1, 2009 |
| A pipelined data processing system includes functional circuitry having a plurality of test points located at predetermined circuit nodes within the functional circuitry, at least one staging storage element associated with a pipeline stage of the data processing system which is coupled |
| 7617437 |
Error correction device and method thereof |
November 10, 2009 |
| A device for error correction includes a memory control module to disable error processing for a memory location depending on the state of a status indicator. The status indicator can be set so that error processing is disabled when valid error correction and detection information for th |
| 7610466 |
Data processing system using independent memory and register operand size specifiers and method |
October 27, 2009 |
| Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate |
| 7584344 |
Instruction for conditionally yielding to a ready thread based on priority criteria |
September 1, 2009 |
| An integrated circuit (10) has a conditional yield instruction (305) which may be used to conditionally yield execution of a currently active thread based on priority and status of other threads. In one embodiment, an I bit 304 may be used to designate whether the priority selection bits |
| 7581151 |
Method and apparatus for affecting a portion of an integrated circuit |
August 25, 2009 |
| In one embodiment, an integrated circuit which uses one or more re-useable modules may use a signature generated by a duplicate state machine or an unmodified state machine to select, control, or otherwise affect a resource on the integrated circuit, where affecting the resource was not |
| 7574564 |
Replacement pointer control for set associative cache and method |
August 11, 2009 |
| A set associative cache includes a plurality of sets, where each set has a plurality of ways. The set associative cache has a plurality of replacement pointers where each set of the plurality of sets has a corresponding replacement pointer within the plurality of replacement pointers |
| 7565514 |
Parallel condition code generation for SIMD operations |
July 21, 2009 |
| A processing system and method performs data processing operations in response to a single data processing instruction. At least two registers store data. First control circuitry compares data in respective corresponding fields of the at least two registers to create a plurality of c |
| 7555605 |
Data processing system having cache memory debugging support and method therefor |
June 30, 2009 |
| A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is exe |
| 7539906 |
System for integrated data integrity verification and method thereof |
May 26, 2009 |
| In accordance with one technique, a first plurality of values associated with data transfers between a processor and a memory is received at the processor and at least a subset of the first plurality of values are accumulated in one or more accumulators. The one or more accumulators are |
| 7500152 |
Apparatus and method for time ordering events in a system having multiple time domains |
March 3, 2009 |
| A system and method time orders events that occur in various portions of the system (10) where different time domains (12, 22, 32) exist. Timestamping circuitry (e.g. 40) is provided in each of a plurality of functional circuits or modules (14, 24, 34). The timestamping circuitry pro |
| 7453756 |
Method for powering an electronic device and circuit |
November 18, 2008 |
| A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alterna |
| 7447886 |
System for expanded instruction encoding and method thereof |
November 4, 2008 |
| A system and methods are discussed for providing additional capabilities to some instructions associated with loop execution. A standard set of instructions is processed using only a standard instruction size. Some loop instructions are processed with a standard instruction portion of |
| 7447867 |
Non-intrusive address mapping having a modified address space identifier and circuitry therefor |
November 4, 2008 |
| A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one external signal generat |
| 7444668 |
Method and apparatus for determining access permission |
October 28, 2008 |
| A method and apparatus for determining access protection (96) includes receiving a plurality of access requests (84) corresponding to a plurality of masters (12, 14), determining access permissions (86), providing state information (60), determining access permissions (86) based on t |
| 7444568 |
Method and apparatus for testing a data processing system |
October 28, 2008 |
| A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user applica |
| 7434264 |
Data processing system with peripheral access protection and method therefor |
October 7, 2008 |
| A flexible peripheral access protection mechanism within a data processing system (10, 100). In one embodiment, each master (14, 15) within the data processing system (10) includes a corresponding privilege level modifier (70, 74) and corresponding trust attributes (71, 72, 75, 76) for |
| 7434108 |
Masking within a data processing system having applicability for a development interface |
October 7, 2008 |
| In current real-time debug systems, debug messages are transmitted through a limited bandwidth port (18) from an integrated circuit (10) to an external development system (25). As some integrated circuits (10) become even more densely packed with multiple bus masters (11, 12) and/or |
| 7430642 |
System and method for unified cache access using sequential instruction information |
September 30, 2008 |
| Techniques for accessing a unified cache to obtain instruction information are provided. One exemplary technique includes accessing, during a first instruction access, a first cache line of a first way of a unified cache having a plurality of ways to obtain instruction information associ |
| 7415558 |
Communication steering for use in a multi-master shared resource system |
August 19, 2008 |
| New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification |
| 7409502 |
Selective cache line allocation instruction execution and circuitry |
August 5, 2008 |
| A processing system and method performs allocation of memory cache lines in response to a cache write miss. A processor receives a plurality of data processing instructions. A first store instruction for storing data in a system memory at a predetermined address is decoded by decoding a |
| 7404019 |
Method and apparatus for endianness control in a data processing system |
July 22, 2008 |
| A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect the endianness or |
| 7401201 |
Processor and method for altering address translation |
July 15, 2008 |
| In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a |
| 7400545 |
Storage circuit with efficient sleep mode and method |
July 15, 2008 |
| A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alterna |
| 7376807 |
Data processing system having address translation bypass and method therefor |
May 20, 2008 |
| In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method thereof. The address translator receives a logical address and converts the logical add |
| 7362645 |
Integrated circuit fuses having corresponding storage circuitry |
April 22, 2008 |
| Storage circuitry (66) may be used to store the values of fuses (77) so that storage circuitry (66) can be read instead of fuses (77). By accessing the fuse values from storage circuitry (66) rather than from fuses (77), there will be no sense current to fuses (77) that may cause mar |
| 7353311 |
Method of accessing information and system therefor |
April 1, 2008 |
| A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority amongst the transact |
| 7340542 |
Data processing system with bus access retraction |
March 4, 2008 |
| A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read |
| 7334059 |
Multiple burst protocol device controller |
February 19, 2008 |
| Multiple burst memory access handling protocols may be implemented at the hardware level or evaluated and selected during design of the hardware. The appropriate burst protocol may be selectable based on burst characteristics such as burst types and the identity of the current bus ma |
| 7315932 |
Data processing system having instruction specifiers for SIMD register operands and method there |
January 1, 2008 |
| Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate |
| 7299335 |
Translation information retrieval transparent to processor core |
November 20, 2007 |
| A system for obtaining translation information from a data processing system transparent to the operation of a processor core of the data processing system. In one embodiment, the processor includes a processor core and memory management circuitry. The memory management circuitry sto |
| 7296137 |
Memory management circuitry translation information retrieval during debugging |
November 13, 2007 |
| A system for obtaining translation information from a data processing system. The system includes circuitry for receiving an external request for translation information. The circuitry determines whether the requested translation information is present in memory management circuitry |
| 7287194 |
Real-time debug support for a DMA device and method thereof |
October 23, 2007 |
| A data processing system (10) has a debug module (26) that selectively generates one or more debug messages that are specific to a Direct Memory Access (DMA) controller device (16) in the system. A control register(70) enables which of the DMA debug messages are provided. The beginning a |
| 7278062 |
Method and apparatus for responding to access errors in a data processing system |
October 2, 2007 |
| In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry |
| 7277972 |
Data processing system with peripheral access protection and method therefor |
October 2, 2007 |
| One embodiment of the present invention provides a flexible peripheral access protection mechanism within a data processing system (10) in order to obtain a more secure operating environment. For example, the data processing system may include a combination of secure (12) and unsecure |
| 7275148 |
Data processing system using multiple addressing modes for SIMD operations and method thereof |
September 25, 2007 |
| Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate |
| 7266848 |
Integrated circuit security and method therefor |
September 4, 2007 |
| The invention relates to an integrated circuit (IC), and more particularly to security to protect an IC (10) against unauthorized accesses. In one embodiment, an identifier is provided external to IC 10. A corresponding input IC security key (52) is then provided to IC 10 and compared to |
| 7249223 |
Prefetching in a data processing system |
July 24, 2007 |
| A method and apparatus is provided for prefetching in a data processing system (10). The data processing system (10) has a bus master (14) and a memory controller (16) coupled to a bus (12). A memory (18) is coupled to the memory controller (16). In the data processing system (14) an add |
| 7248069 |
Method and apparatus for providing security for debug circuitry |
July 24, 2007 |
| The invention relates to debug circuitry (20) and more particularly to a method and apparatus for providing security for debug circuitry (20). In one embodiment, a plurality of non-volatile elements (38) are used in providing selective disabling and re-enabling of at least a portion of |
| 7237149 |
Method and apparatus for qualifying debug operation using source information |
June 26, 2007 |
| A data processing system (10) has a system debug module (19) coupled to a processor (12) for performing system debug functions. Located within the system, and preferably within the processor, is debug circuitry (32) that selectively provides debug information related to the processor. Th |
| 7228401 |
Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or sel |
June 5, 2007 |
| The present invention relates generally to interfacing a processor with at least one coprocessor. One embodiment relates to a processor having a set of broadcast specifiers which it uses to selectively broadcast an operand that is being written to a register within the processor to a cop |
| 7200719 |
Prefetch control in a data processing system |
April 3, 2007 |
| In one embodiment, a data processing system (10) includes a first master, storage circuitry (35) coupled to the first master (12) for use by the first master (12), a first control storage circuit (38) which stores a first prefetch limit (60), a prefetch buffer (42), and prefetch circuitr |
| 7188262 |
Bus arbitration in low power system |
March 6, 2007 |
| Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power state by the processor and the system circuitry and enabling bus arbitration by the processo |
| 7185251 |
Method and apparatus for affecting a portion of an integrated circuit |
February 27, 2007 |
| In one embodiment, an integrated circuit which uses one or more re-useable modules may use a signature generated by a duplicate state machine or an unmodified state machine to select, control, or otherwise affect a resource on the integrated circuit, where affecting the resource was not |
| 7185148 |
Read access and storage circuitry read allocation applicable to a cache |
February 27, 2007 |
| A read allocation indicator (e.g. read allocation signal 30) is provided to storage circuitry (e.g. cache 22) to selectively determine whether read allocation will be performed for the read access. Read allocation may include modification of the information content of the cache (22) |
| 7185121 |
Method of accessing memory via multiple slave ports |
February 27, 2007 |
| A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port |
| 7155618 |
Low power system and method for a data processing system |
December 26, 2006 |
| Systems and methods are discussed to identify a recoverable state in a low power device. A low power device having an arbiter to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller within the low power device prov |
| 7139878 |
Method and apparatus for dynamic prefetch buffer configuration and replacement |
November 21, 2006 |
| A memory controller and method thereof configures a prefetch buffer dynamically for interfacing between multiple bus masters of different burst support and multiple memories having different characteristics. A line size of at least a portion of the prefetch buffer is modified based u |
| 7130943 |
Data processing system with bus access retraction |
October 31, 2006 |
| A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read |
| 7124281 |
Processing system having sequential address indicator signals |
October 17, 2006 |
| Embodiments of the present inventions relate to processors having sequential address indicator signals, also referred to as sequence signals, for indicating when accessed addresses are sequential. One embodiment relates to a processing system for accessing memory having an address bu |
| 7117346 |
Data processing system having multiple register contexts and method therefor |
October 3, 2006 |
| A data processing system having multiple register contexts is described. One embodiment of the present invention uses a user programmable context control register for each of the multiple register contexts to allow for the mapping of portions of an alternate register context into a curre |
