The present invention utilizes a single DMA engine to process the requests of active DMA channels competing for transfer of data over a single bus. The invention employs two identical sets of DMA request registers which are connected to a processor. These register sets are connected thro
The present invention provides a method and apparatus for improving the synchronization of timing signals in a system where firmware is being employed. In particular, the present invention enables the firmware to generate signals with a timing that is required by a hardware protocol.