| Patent Number |
Title Of Patent |
Date Issued |
| 6885599 |
Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device |
April 26, 2005 |
| By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a |
| 6754133 |
Semiconductor device |
June 22, 2004 |
| A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced |
| 6711075 |
Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device |
March 23, 2004 |
| By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a |
| 6707139 |
Semiconductor device with plural unit regions in which one or more MOSFETs are formed |
March 16, 2004 |
| A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is |
| 6680869 |
Semiconductor device |
January 20, 2004 |
| A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a se |
| 6549484 |
Semiconductor device |
April 15, 2003 |
| An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparin |
| 6483349 |
Semiconductor integrated circuit device |
November 19, 2002 |
| Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bi |
| 6407963 |
Semiconductor memory device of DDR configuration having improvement in glitch immunity |
June 18, 2002 |
| A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a se |
| 6339344 |
Semiconductor integrated circuit device |
January 15, 2002 |
| Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bi |
| 6335901 |
Semiconductor device |
January 1, 2002 |
| An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparin |
| 6274895 |
Semiconductor integrated circuit device |
August 14, 2001 |
| A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is |
| 6271687 |
Sense amplifier circuit |
August 7, 2001 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
| 5963483 |
Synchronous memory unit |
October 5, 1999 |
| A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the |
| 5936909 |
Static random access memory |
August 10, 1999 |
| A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address sel |
| 5854562 |
Sense amplifier circuit |
December 29, 1998 |
| A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the |
