| Patent Number |
Title Of Patent |
Date Issued |
| 5783936 |
Temperature compensated reference current generator |
July 21, 1998 |
| A temperature compensated resistance current generator. The generator provides temperature compensated reference current in a digital CMOS environment where resistors with positive temperature coefficients are not available, and where temperature coefficients are large. The current g |
| 5760640 |
Highly symmetrical bi-direction current sources |
June 2, 1998 |
| A bi-directional current source which maintains accurate, substantially equal source and sink currents over a large range of output voltages. The current source includes a primary field effect transistor (FET) and two mirroring FET's. It additionally includes at least one operational |
| 5381046 |
Stacked conductive resistive polysilicon lands in multilevel semiconductor chips |
January 10, 1995 |
| A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick |
| 5320975 |
Method of forming thin film pseudo-planar FET devices and structures resulting therefrom |
June 14, 1994 |
| A method of forming thin film pseudo-planar polysilicon gate PFETs (pPFETs) simultaneously with bulk PFET and NFET devices in a CMOS or BiCMOS semiconductor structure, comprising the steps of: providing a P-type silicon substrate having a surface that includes a plurality of isolation |
| 5275963 |
Method of forming stacked conductive and/or resistive polysilicon lands in multilevel semiconduc |
January 4, 1994 |
| A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formedthereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact |
| 5112765 |
Method of forming stacked tungsten gate PFET devices and structures resulting therefrom |
May 12, 1992 |
| A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysil |
| 5100817 |
Method of forming stacked self-aligned polysilicon PFET devices and structures resulting therefr |
March 31, 1992 |
| A stacked semiconductor structure including a base structure (18/19) is comprised of a semiconductor substrate having active regions (21) of devices (N1, . . . ) formed therein and/or a plurality of polysilicon lines (23-1, . . . ) formed thereupon; a first thick passivating layer (2 |
