| Patent Number |
Title Of Patent |
Date Issued |
| 7555632 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
June 30, 2009 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 7487333 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
February 3, 2009 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 7343473 |
System and method for translating non-native instructions to native instructions for processing |
March 11, 2008 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a p |
| 7162610 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
January 9, 2007 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 7028161 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
April 11, 2006 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 6986024 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
January 10, 2006 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6959375 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
October 25, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6954847 |
System and method for translating non-native instructions to native instructions for processing |
October 11, 2005 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 6948052 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
September 20, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6941447 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
September 6, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6934829 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 23, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6915412 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
July 5, 2005 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6647485 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
November 11, 2003 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6282630 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
August 28, 2001 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 6272619 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 7, 2001 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6263423 |
System and method for translating non-native instructions to native instructions for processing |
July 17, 2001 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 6256720 |
High performance, superscalar-based computer system with out-of-order instruction execution |
July 3, 2001 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6128723 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
October 3, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6101594 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
August 8, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6092181 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
July 18, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6038654 |
High performance, superscalar-based computer system with out-of-order instruction execution |
March 14, 2000 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 6038653 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
March 14, 2000 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 5983334 |
Superscalar microprocessor for out-of-order and concurrently executing at least two RISC instruc |
November 9, 1999 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 5961629 |
High performance, superscalar-based computer system with out-of-order instruction execution |
October 5, 1999 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The |
| 5832292 |
High-performance superscalar-based computer system with out-of-order instruction execution and c |
November 3, 1998 |
| The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of funct |
| 5828861 |
System and method for reducing the critical path in memory control unit and input/output control |
October 27, 1998 |
| A system and method for eliminating the critical path of a processor-based system by sending a signal to transition memory and/or I/O control units to a READ/WRITE state prior to the end of the complete instruction decode. If the decoding phase of the opcode of the instruction reveals th |
| 5689720 |
High-performance superscalar-based computer system with out-of-order instruction execution |
November 18, 1997 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instr |
| 5619666 |
System for translating non-native instructions to native instructions and combining them into a |
April 8, 1997 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 5560032 |
High-performance, superscalar-based computer system with out-of-order instruction execution and |
September 24, 1996 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program ins |
| 5546552 |
Method for translating non-native instructions to native instructions and combining them into a |
August 13, 1996 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 5539911 |
High-performance, superscalar-based computer system with out-of-order instruction execution |
July 23, 1996 |
| A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instr |
| 5481685 |
RISC microprocessor architecture implementing fast trap and exception state |
January 2, 1996 |
| Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler c |
| 5448705 |
RISC microprocessor architecture implementing fast trap and exception state |
September 5, 1995 |
| A method for use in a microprocessor to return execution to a main program after processing an interruption to the sequential processing of instructions from the main instruction stream is disclosed. The method comprises fetching instructions from a main instruction stream to a main |
| 5438668 |
System and method for extraction, alignment and decoding of CISC instructions into a nano-instru |
August 1, 1995 |
| A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a porti |
| 5297287 |
System and method for resetting a microprocessor system |
March 22, 1994 |
| The present invention provides a reset circuit with two different threshold input voltages. The reset circuit of the present invention is located within a processor, and is designed to control the reset functions of both the processor and the chips located peripheral to the processor. Th |
