| Patent Number |
Title Of Patent |
Date Issued |
| 7498219 |
Methods for reducing capacitor dielectric absorption and voltage coefficient |
March 3, 2009 |
| Semiconductor devices and fabrication methods are provided in which a capacitor dielectric is provided with phosphorus or other n-type dopants through implantation of other techniques to reduce the voltage coefficient of capacitance and/or the dielectric absorption of the capacitor. |
| 7396722 |
Memory device with reduced cell area |
July 8, 2008 |
| The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second act |
| 7307309 |
EEPROM with etched tunneling window |
December 11, 2007 |
| A method forming a current path in a substrate (322) having a first conductivity type is disclosed. The method includes forming an impurity region (314) having a second conductivity type and extending from a face of the substrate to a first depth. A hole (305) is formed in the impurity |
| 7244651 |
Fabrication of an OTP-EPROM having reduced leakage current |
July 17, 2007 |
| The leakage current of an OTP-EPROM cell formed using buried channel PMOS technology can be reduced. The reduction in leakage current of the OTP-EPROM can be achieved by blocking implantation of the V.sub.tp implant into a channel region of an n-well that substantially underlies a fl |
| 7166903 |
Drain extended MOS transistors with multiple capacitors and methods of fabrication |
January 23, 2007 |
| Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductiv |
| 7157784 |
Drain extended MOS transistors with multiple capacitors and methods of fabrication |
January 2, 2007 |
| Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductiv |
| 7060556 |
Drain extended MOS transistors with multiple capacitors and methods of fabrication |
June 13, 2006 |
| Multi-capacitor drain extended transistor devices and methods are provided. A first capacitor structure comprises a first dielectric layer (14) and a first gate layer (16) and first and second lateral sides. The first capacitor structure overlies a channel region of a first conductiv |
| 7045418 |
Semiconductor device including a dielectric layer having a gettering material located therein an |
May 16, 2006 |
| The present invention provides a semiconductor device (200), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device (200) includes a floating gate (230) located over a semiconductor substrate (210), wher |
| 7019356 |
Memory device with reduced cell area |
March 28, 2006 |
| The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second act |
| 6424005 |
LDMOS power device with oversized dwell |
July 23, 2002 |
| An LDMOS device (10, 20, 50, 60) that is made with minimal feature size fabrication methods, but overcomes potential problems of misaligned Dwells (13). The Dwell (13) is slightly overstated so that its n-type dopant is implanted past the source edge of the gate region (18), which permit |
