| Patent Number |
Title Of Patent |
Date Issued |
| 7554382 |
Method for reducing insertion loss and providing power down protection for MOSFET switches |
June 30, 2009 |
| An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power supply or signal level |
| 7514983 |
Over-voltage tolerant pass-gate |
April 7, 2009 |
| A pass-gate having a single or parallel opposite polarity FETs is disclosed. The wells of the primary transistor switches are driven from circuitry that reduces over-voltage leakage and other malfunctions. A circuit that drives the wells is also used to power enable circuits that dri |
| 7095266 |
Circuit and method for lowering insertion loss and increasing bandwidth in MOSFET switches |
August 22, 2006 |
| A DC symmetrical FET switch includes second and third switches connecting the well of the symmetrical FET switch to the drains and the source when the symmetrical FET switch is on. When the three FET's are on, the well, source and drain of the symmetric FET switch all exhibit the same in |
| 6774675 |
Bus hold circuit with power-down and over-voltage tolerance |
August 10, 2004 |
| A bus hold circuit of CMOS components that draws no DC current and is over voltage tolerant is described. No leakage current is drawn from the input when the input voltage is greater than the bus hold circuit supply voltage. A feedback inverter is used to s latch the Vin logic in the bus |
| 6236259 |
Active undershoot hardened fet switch |
May 22, 2001 |
| A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a differential logic sense circuit that |
| 5963080 |
Undershoot hardened FET switch |
October 5, 1999 |
| A bus switch for transferring logic signals between nodes without the problems associated with undershoot conduction. The bus switch is an FET switch including a single primary transfer transistor. The bulk of the transfer transistor is coupled to a bulk regulating circuit including a |
