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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Mirgorodski; Yuri
Address:
Sunnyvale, CA
No. of patents:
45
Patents:












Patent Number Title Of Patent Date Issued
8247862 Method of enhancing charge storage in an E.sup.2PROM cell August 21, 2012
A method is provided for enhancing charge storage in an E.sup.2PROM cell structure that includes a read transistor having spaced apart source an drain diffusion regions formed in a semiconductor substrate to define a substrate channel region therebetween, a conductive charge storage
8207578 Method of forming a region of graded doping concentration in a semiconductor device and related June 26, 2012
A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and
8183621 Non-volatile memory cell having a heating element and a substrate-based control gate May 22, 2012
The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase volta
7978519 Method of reading an NVM cell that utilizes a gated diode July 12, 2011
A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel re
7969790 Method of erasing an NVM cell that utilizes a gated diode June 28, 2011
A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel
7964485 Method of forming a region of graded doping concentration in a semiconductor device and related June 21, 2011
A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and
7919807 Non-volatile memory cell with heating element April 5, 2011
The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase volta
7919805 Non-volatile memory cell with two capacitors and one PNP transistor and a method of forming such April 5, 2011
In a non-volatile memory cell, a single poly SOI technology is used to save space and achieve low current programming by providing two capacitors formed in an n-material over an NBL, forming a inverter in an n-material over a PBL, and isolating the NBL from the PBL by means of a ligh
7911869 Fuse-type memory cells based on irreversible snapback device March 22, 2011
In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.
7859912 Mid-size NVM cell and array utilizing gated diode for low current programming December 28, 2010
A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also
7719048 Heating element for enhanced E.sup.2PROM May 18, 2010
A heating element is utilized to improve the bias conditions of an E.sup.2PROM cell during program and erase operations. The heating element can also be used to anneal or condition the cell for improved charge storage. During a program or an erase operation, the cell's control gate a
7705403 Programmable ESD protection structure April 27, 2010
In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as des
7663173 Non-volatile memory cell with poly filled trench as control gate and fully isolated substrate as February 16, 2010
In a non-volatile memory cell, charge is stored in a fully isolated substrate or floating bulk that forms a storage capacitor with a first poly strip and includes a second poly strip defining a read gate and a poly-filled trench defining a control gate.
7651913 Method of forming non-volatile memory (NVM) retention improvement utilizing protective electrica January 26, 2010
An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second po
7651897 Integrated circuit with metal heat flow path coupled to transistor and method for manufacturing January 26, 2010
A method for manufacturing a chip with a metal heat flow path extending between a terminal of a transistor thereof and bulk semiconductor material of the chip (e.g., from the terminal to a substrate over which the transistor is formed or to the body of a semiconductor device adjacent
7435628 Method of forming a vertical MOS transistor October 14, 2008
A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transis
7425741 EEPROM structure with improved data retention utilizing biased metal plate and conductive layer September 16, 2008
A biased conductive plate is provided over an NVM cell structure to overcome data retention charge loss due to the presence of dielectric films that are conductive at higher temperatures. The biased conductive plate is preferably formed from the lowest metal layer in the fabrication
7422952 Method of forming a BJT with ESD self protection September 9, 2008
A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting
7375393 Non-volatile memory (NVM) retention improvement utilizing protective electrical shield May 20, 2008
An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second po
7339835 Non-volatile memory structure and erase method with floating gate voltage control March 4, 2008
Feedback between the floating gate voltage and a high erase voltage is utilized in the erase operation of a non-volatile memory (NVM) cell. Erasing stops when the floating gate voltage reaches the threshold voltage of the controlling transistor, making the variability of the NVM cell
7298653 Reducing cross die variability in an EEPROM array November 20, 2007
In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read vo
7298599 Multistage snapback ESD protection network November 20, 2007
A snapback ESD protection network coupled across first and second integrated circuit pads and including first and second snapback devices, such as SCR devices, with the second device having a turnoff current I.sub.TOFF which is greater than the turnoff current of the first device. Ea
7262401 Active pixel sensor cell with integrating varactor and method for using such cell August 28, 2007
An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure
7259411 Vertical MOS transistor August 21, 2007
A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transis
7233521 Apparatus and method for storing analog information in EEPROM memory June 19, 2007
A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is coupled to receive the a
7221036 BJT with ESD self protection May 22, 2007
A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting
7209503 Laser powered integrated circuit April 24, 2007
An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive
7180379 Laser powered clock circuit with a substantially reduced clock skew February 20, 2007
A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents
7180133 Method and structure for addressing hot carrier degradation in high voltage devices February 20, 2007
In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including
7141831 Snapback clamp having low triggering voltage for ESD protection November 28, 2006
An SCR device having a first P type region disposed in a semiconductor body and electrically connected to anode terminal of the device. At least one N type region is also disposed in the body adjacent the first P type region so as to form a PN junction having a width Wn near a surface of
7113427 NVM PMOS-cell with one erased and two programmed states September 26, 2006
NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two
7102117 Active pixel sensor cell with integrating varactor and method for using such cell September 5, 2006
An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure
7075341 Low area linear time-driver circuit July 11, 2006
A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.
7057867 Electrostatic discharge (ESD) protection clamp circuitry June 6, 2006
Electrostatic discharge (ESD) protection clamp circuitry including current tunneling circuitry to provide control current for controlling current shunting circuitry for shunting ESD current from the protected signal terminal.
7050314 LVTSCR charge pump converter circuit May 23, 2006
A charge pump circuit in which at least one of the switching elements takes the form of a LVTSCR. The switching on and off of the LVTSCRs may be achieved by making use of a pulsed input and relying on the triggering and holding voltages of the LVTSCRs to switch on and off.
7042763 Programming method for nonvolatile memory cell May 9, 2006
A method of selectively programming nonvolatile memory cells in which multiple programming voltages are used to obtain the desired voltage on the storage nodes of the cells selected for programming, while the storage nodes of unselected cells remain undisturbed.
7020027 Programming method for nonvolatile memory cell March 28, 2006
A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node.
6992927 Nonvolatile memory cell January 31, 2006
An integrated nonvolatile memory circuit having a plurality of control devices. Separate devices execute distinct control, erase, write and read operations, thereby allowing each device to be individually selected and optimized for performing its respective operation.
6985386 Programming method for nonvolatile memory cell January 10, 2006
A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node.
6982907 Retention improvement technique for one time programmable non-volatile memory January 3, 2006
A programming technique for a one-time-programmable non-volatile memory (NVM) utilizes a repeated programming cycle with an interval between cycles that is long enough to redistribute charge in the layers surrounding the floating gate of the cell. Each cycle programs the floating gat
6947331 Method of erasing an EEPROM cell utilizing a frequency/time domain based erased signal September 20, 2005
A method is provided for erasing a nonvolatile memory cell that includes a source region, a drain region, a floating gate electrode and a control gate electrode to which an erase signal is applied. In accordance with the method, a source bias voltage is applied to the source region, a dr
6903979 Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of subs June 7, 2005
A method of programming a PMOS stacked gate memory cell is provided that utilizes the correlation between injection current and substrate current during the programming cycle to provide a feedback correction to the control gate of the memory cell to compensate for the negative potential
6903978 Method of PMOS stacked-gate memory cell programming enhancement utilizing stair-like pulses of c June 7, 2005
A method of programming a PMOS stacked gate memory cell is provided that utilizes a sequence of control gate pulses to obtain the desired potential on the floating gate.
6862216 Non-volatile memory cell with gated diode and MOS transistor and method for using such cell March 1, 2005
A non-volatile memory cell including a gated diode and a single readout transistor, methods for programming and reading out such a cell, and a memory including an array of such cells. The readout transistor is an MOS transistor. The transistor and gated diode are formed in a volume of
6806529 Memory cell with a capacitive structure as a control gate and method of forming the memory cell October 19, 2004
In an electrically programmable non-volatile memory cell, the first terminal of a high density capacitive structure is electrically connected to a conductive structure to form a floating gate/first electrode, while the second terminal of the capacitive structure is used as a control gate










 
 
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