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Inventor:
Miller; Michael J.
Address:
Saratoga, CA
No. of patents:
14
Patents:












Patent Number Title Of Patent Date Issued
7889727 Switching circuit implementing variable string matching February 15, 2011
A content matching engine (CME) uses a content addressable memory (CAM) array that stores a plurality of strings in separate entries. The strings define one or more rules to be matched. The strings of each rule are linked, thereby providing a required order. The strings of each rule can
7353332 Switching circuit implementing variable string matching April 1, 2008
A content matching engine (CME) uses a content addressable memory (CAM) array that stores a plurality of strings in separate entries. The strings define one or more rules to be matched. The strings of each rule are linked, thereby providing a required order. The strings of each rule can
7290084 Fast collision detection for a hashed content addressable memory (CAM) using a random access mem October 30, 2007
A hardware hashing circuit is configured to perform a hashing function on a received character string, thereby creating a hashed output value and a collision resolution value. A content addressable memory (CAM) receives the hashed output value, and in response, provides an index value an
6996662 Content addressable memory array having flexible priority support February 7, 2006
A method for processing addresses having variable prefix lengths, including (1) applying an input address to a plurality of CAM blocks; (2) assigning different sets of CAM blocks to store prefixes of different lengths; (3) generating a hit signal and an index signal with each of the
6700827 Cam circuit with error correction March 2, 2004
A CAM circuit including a RAM array, a CAM array, a control/interface circuit, and an error detection and correction (EDC) circuit. The control/interface circuit systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually refreshing d
6560156 CAM circuit with radiation resistance May 6, 2003
A CAM circuit including a RAM array, a CAM array, and a control circuit that systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually restoring data that has been corrupted by radiation. The RAM and CAM arrays can be formed on the same
6137779 Transmission rate calculation scheme using table-lookup October 24, 2000
A method for distributing the available bit rates in a variable bit rate service under asynchronous transfer mode is provided by distributing the available bit rates in logarithmic-linear steps, so that the ratio between two successive available bit rates are substantially constant. To m
5987031 Method for fair dynamic scheduling of available bandwidth rate (ABR) service under asynchronous November 16, 1999
A method for dynamic scheduling of data transmission for a large number of data channels under the available bit rate (ABR) service protocols of asynchronous transfer mode (ATM) uses a schedule table and ready queue. In this method, at each time slot, data channels referenced in the curr
5796735 System and method for transmission rate control in a segmentation and reassembly (SAR) circuit u August 18, 1998
A segmentation and reassembly circuit under the ATM standard uses a transmit cell schedule table (TCST) to support real time transmission of ATM cells in multiple constant bit rate virtual channels. In one embodiment, null cells are intentionally scheduled in a TCST. Transmission of
5581564 Diagnostic circuit December 3, 1996
A diagnostic circuit of the present invention has serial command input and output pins separate from its serial data input and output pins. In one embodiment, the diagnostic circuit has one command register and one data register, the data register receiving serially an input signal and
5331645 Expandable digital error detection and correction device July 19, 1994
A pair of similar, 32-bit, error detection and correction devices, including a "lower 32-bit" device (210) and an "upper 32-bit" device (212) are configured as a 64-bit, error detection and correction system. When a (64-bit) word of data is being stored in memory, the lower 32-bit device
5175859 Apparatus for disabling unused cache tag input/output pins during processor reset by sensing pul December 29, 1992
A method of programming a cache tag comparator by designing a semiconductor device's internal circuitry such that an input/output pin of the device may be programmed by an external resistor to ground that will indicate during the reset phase of the device that an alternate function for t
5099481 Registered RAM array with parallel and serial interface March 24, 1992
A serial protocol register and an initialization counter are configured to initialize (program) a RAM array. The register is configured to receive, in serial format, an initial address to be loaded into the counter. Also, the register is configured to receive, in serial format, a series
5079693 Bidirectional FIFO buffer having reread and rewrite means January 7, 1992
A FIFO buffer in accordance with the present invention employs a 1K by eighteen FIFO (A.fwdarw.B) buffer portion to store eighteen-bit words; an eighteen-bit-to-nine-bit multiplexer portion to convert (fold) stored eighteen-bit words into two, nine-bit words; a nine-bit-to-sixteen-bit










 
 
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