| Patent Number |
Title Of Patent |
Date Issued |
| 6785188 |
Fully synchronous pipelined RAM |
August 31, 2004 |
| A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input cir |
| 6591354 |
Separate byte control on fully synchronous pipelined SRAM |
July 8, 2003 |
| A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corre |
| 6567338 |
Fully synchronous pipelined RAM |
May 20, 2003 |
| A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input cir |
| 6470418 |
Pipelining a content addressable memory cell array for low-power operation |
October 22, 2002 |
| A content addressable memory (CAM) system that includes first and second CAM arrays, which generate first and second sets of match control signals, respectively, having higher and lower priorities, respectively. The first CAM array is enabled during a first memory cycle, and the first se |
| 6370613 |
Content addressable memory with longest match detect |
April 9, 2002 |
| A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including eithe |
| 6249480 |
Fully synchronous pipelined ram |
June 19, 2001 |
| A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input cir |
| 6115320 |
Separate byte control on fully synchronous pipelined SRAM |
September 5, 2000 |
| A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corre |
| 6094399 |
Fully synchronous pipelined RAM |
July 25, 2000 |
| A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input cir |
| 6081478 |
Separate byte control on fully synchronous pipelined SRAM |
June 27, 2000 |
| A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corre |
| 5950233 |
Interleaved burst address counter with reduced delay between rising clock edge and burst address |
September 7, 1999 |
| A burst address sequencer and method for providing sequential addresses to a memory which operates in response to a clock signal. The burst address sequencer includes a plurality of two-stage address registers, with an address register being provided for each address bit. Prior to an ini |
| 5920580 |
Multiple error detection in error detection correction circuits |
July 6, 1999 |
| A multi-error detector uses single byte error correcting-double byte error detecting codes but detects some multiple errors including double, triple, quadruple and more errors in a code. To detect the multiple errors, the multi-error detectors uses error pointer and a syndrome which are |
| 5875151 |
Fully synchronous pipelined ram |
February 23, 1999 |
| A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input cir |
| 5841732 |
Fully synchronous pipelined ram |
November 24, 1998 |
| A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input cir |
| 5838631 |
Fully synchronous pipelined ram |
November 17, 1998 |
| A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input cir |
| 5828606 |
Fully synchronous pipelined RAM |
October 27, 1998 |
| A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input cir |
| 5807136 |
Space saving connector layout |
September 15, 1998 |
| Two connectors located directly opposite each other on opposite sides of a printed circuit board are attached together and to the circuit board by means of keys integral to the connectors. |
