| Patent Number |
Title Of Patent |
Date Issued |
| 7592849 |
Level shifter for semiconductor memory device implemented with low-voltage transistors |
September 22, 2009 |
| A level shifter is proposed. The level shifter includes a stage having a first branch and a second branch, each branch including: a selection terminal for receiving a selection signal, the selection signal received by the first branch and the second branch being alternatively at a first |
| 7581153 |
Memory with embedded error correction codes |
August 25, 2009 |
| A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory |
| 7532061 |
Charge-pump type, voltage-boosting device with reduced ripple, in particular for non-volatile fl |
May 12, 2009 |
| Voltage-boosting device having a supply input receiving a supply voltage, and a high-voltage output. The device is formed by a plurality of charge-pump stages series-connected between the supply input and the high-voltage output. Each charge-pump stage has a respective enabling input |
| 7521983 |
High-voltage switch with low output ripple for non-volatile floating-gate memories |
April 21, 2009 |
| A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the ch |
| 7499332 |
Circuit and method for electrically programming a non-volatile semiconductor memory via an addit |
March 3, 2009 |
| A method of electrically programming a memory cell includes: applying at least one electrical programming pulse to the memory cell; verifying the reaching of a target programming state by the memory cell; and repeating the acts of applying and verifying until the reaching of a target |
| 7444543 |
Data control unit capable of correcting boot errors, and corresponding self-correction method |
October 28, 2008 |
| A boot method for a data control unit downloads boot information from a nonvolatile memory into a temporary buffer of a boot-activation unit. A processing unit is activated by the boot-activation unit; a boot code is executed by the processing unit; and an operating code is downloaded fr |
| 7394694 |
Flash memory device with NAND architecture with reduced capacitive coupling effect |
July 1, 2008 |
| A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory |
| 7382660 |
Method for accessing a multilevel nonvolatile memory device of the flash NAND type |
June 3, 2008 |
| Multi-level programming allows for writing a first and a second bit in selected cells by separately programming the first bit from the second bit. Programming of the first bit determines a shifting from a first threshold level to a second threshold level. Programming of the second bi |
| 7362616 |
NAND flash memory with erase verify based on shorter evaluation time |
April 22, 2008 |
| A non-volatile memory device is proposed. The non-volatile memory device includes a plurality of memory cells each one having a programmable threshold voltage, and means for reading a set of selected memory cells with respect to a plurality of reference voltages, for each selected me |
| 7349265 |
Reading method of a NAND-type memory device and NAND-type memory device |
March 25, 2008 |
| A reading method of a NAND memory device includes the steps of first connecting a first end terminal of a stack of cells to a reference line, second connecting a second end terminal of the stack of cells to a respective bitline, and charging the bitline to a predetermined bitline rea |
| 7336538 |
Page buffer circuit and method for multi-level NAND programmable memories |
February 26, 2008 |
| A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first |
| 7328397 |
Method for performing error corrections of digital information codified as a symbol sequence |
February 5, 2008 |
| A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion |
| 7260005 |
Data bus architecture for a semiconductor memory |
August 21, 2007 |
| A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associa |
| 7221602 |
Memory system comprising a semiconductor memory |
May 22, 2007 |
| A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises |
| 7221212 |
Trimming functional parameters in integrated circuits |
May 22, 2007 |
| A trimming structure for trimming functional parameters of an Integrated Circuit--IC--(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are resp |
| 7184348 |
Sensing circuit for a semiconductor memory |
February 27, 2007 |
| A sensing circuit is provided for sensing semiconductor memory cells. The sensing circuit includes at least one first circuit branch, a feedback-controlled circuit element in the first circuit branch, a current-to-voltage conversion circuit in the first branch, and at least one compa |
| 7184319 |
Method for erasing non-volatile memory cells and corresponding memory device |
February 27, 2007 |
| The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array organized in a row-and-column layout, and divided in |
| 7068540 |
Method and device for programming an electrically programmable non-volatile semiconductor memory |
June 27, 2006 |
| A device and method for programming an electrically programmable memory applies at least one first programming pulse to a group of memory cells (MC1 MCk) of the memory, accesses the memory cells of the group to ascertain a programming state thereof, and applies at least one second pr |
| 7035142 |
Non volatile memory device including a predetermined number of sectors |
April 25, 2006 |
| The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it act |
| 7031193 |
Method and device for programming an electrically programmable non-volatile semiconductor memory |
April 18, 2006 |
| A device and method for programming an electrically programmable memory accesses a group of memory cells (MC1 MCk) of the memory to ascertain a programming state thereof (401,407;503,509a,513a); applies a programming pulse to those memory cells in the group whose programming state is not |
| 7017099 |
Method for error control in multilevel cells with configurable number of stored bits |
March 21, 2006 |
| A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a num |
| 6956773 |
Circuit for programming a non-volatile memory device with adaptive program load control |
October 18, 2005 |
| A circuit (115,145,150), for programming a non-volatile memory device (100) having a plurality of memory cells (105), includes a plurality of driving elements (115) each one for applying a program pulse to a selected memory cell to be programmed. The driving elements are suitable to be s |
| 6947329 |
Method for detecting a resistive path or a predetermined potential in non-volatile memory electr |
September 20, 2005 |
| The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding |
| 6944072 |
Self-repair method for nonvolatile memory devices with erasing/programming failure, and relative |
September 13, 2005 |
| The memory device has a memory block, formed by a plurality of standard sectors and a redundancy portion; a control circuit, which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit for the data stored in the memory cells. The correctnes |
| 6922366 |
Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolat |
July 26, 2005 |
| A self-repair method intervenes at the end of an operation of modification of a nonvolatile memory, selected between programming and erasing, in the event of detection of just one non-functioning cell, and carries out redundancy of the non-functioning cell. To this end, the memory array |
| 6901011 |
Self-repair method via ECC for nonvolatile memory devices, and relative nonvolatile memory devic |
May 31, 2005 |
| The method for using a nonvolatile memory (1) having a plurality of cells (14), each of which stores a datum, is based upon the steps of performing an modification operation of erasing/programming (22) the data of the memory; verifying (23) the correctness of the data of the memory cells |
| 6891755 |
Architecture for a flash-EEPROM simultaneously readable in other sectors while erasing and/or pr |
May 10, 2005 |
| A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sec |
| 6871258 |
METHOD FOR ERASING AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-F |
March 22, 2005 |
| Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a pl |
| 6836442 |
Nonvolatile memory device having a voltage booster with a discharge circuit activated during sta |
December 28, 2004 |
| A voltage booster device to selectively assume an active status and a stand-by status with a first terminal to assume a respective electric potential and associated to a first capacitor, a second terminal associated to a second capacitor and selectively connectable to the first termi |
| 6829168 |
Power supply circuit structure for a row decoder of a multilevel non-volatile memory device |
December 7, 2004 |
| A power supply circuit structure is useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the |
| 6822905 |
Regulation method for the source terminal voltage in a non-volatile memory cell during a program |
November 23, 2004 |
| A method and a circuit are for regulating the source terminal voltage of a non-volatile memory cell during the cell programming and/or reading phases. The method includes a phase of locally regulating the voltage value and includes comparing the source current of the cell array with a |
| 6809961 |
Regulation method for the drain, body and source terminals voltages in a non-volatile memory cel |
October 26, 2004 |
| A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least |
| 6788579 |
Method for programming nonvolatile memory cells with program and verify algorithm using a stairc |
September 7, 2004 |
| A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the nex |
| 6728141 |
Method and circuit for timing dynamic reading of a memory cell with control of the integration t |
April 27, 2004 |
| The method for timing reading of a memory cell envisages supplying the memory cell (with a constant current by means of a first capacitive element, integrating said current in a time interval, and controlling the duration of the time interval in such a way as to compensate for any de |
| 6724658 |
Method and circuit for generating reference voltages for reading a multilevel memory cell |
April 20, 2004 |
| The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell and a second memory cell respectively having a first reference programming level and a second reference programming level; a first reference circuit and a second |
| 6674385 |
Analog-to-digital conversion method and device, in high-density multilevel non-volatile memory d |
January 6, 2004 |
| An analog-to-digital conversion method and device for a multilevel non-volatile memory device that includes a multilevel memory cell. The method comprises a first step of converting the most significant bits contained in the memory cell, followed by a second step of converting the le |
| 6650173 |
Programmable voltage generator |
November 18, 2003 |
| The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. T |
| 6646913 |
Method for storing and reading data in a multilevel nonvolatile memory |
November 11, 2003 |
| The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a number of bits that is not an integer power of two, for example three. In this way, one data byte is stored in a |
| 6643179 |
Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile |
November 4, 2003 |
| The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell by a capacitive element. The capacitive element is initially charged and then discharged linearly in a preset time, while the memory cell is biased at a constant voltage. In |
| 6642776 |
Bandgap voltage reference circuit |
November 4, 2003 |
| Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a |
| 6639833 |
Method and circuit for dynamic reading of a memory cell at low supply voltage and with low outpu |
October 28, 2003 |
| The method for reading a memory cell includes supplying the cell with a first charge quantity through a capacitive integration element and reintegrating the first charge quantity through a plurality of second charge quantities supplied alternately and in succession to the capacitive |
| 6603681 |
Method of pulse programming, in particular for high-parallelism memory devices, and a memory dev |
August 5, 2003 |
| A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a v |
| 6574146 |
Circuit and method for timing multi-level non-volatile memories |
June 3, 2003 |
| A read timing circuit regulates the step of reading from a multi-level non-volatile memory, which circuit is of a type adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path including at least one dummy wordline, the latter being appli |
| 6559627 |
Voltage regulator for low-consumption circuits |
May 6, 2003 |
| A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output termina |
| 6542404 |
Small size, low consumption, multilevel nonvolatile memory |
April 1, 2003 |
| A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (V.sub.DD), a voltage boosting circuit (26) supplying a boosted voltage (V.sub.p), higher than the supply voltage (V.sub.DD), a boosted line (30) connected to the voltage boosting circuit (26) and a |
| 6532171 |
Nonvolatile semiconductor memory capable of selectively erasing a plurality of elemental memory |
March 11, 2003 |
| A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective |
| 6515911 |
Circuit structure for providing a hierarchical decoding in semiconductor memory devices |
February 4, 2003 |
| A circuit device structured to enable a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and including a matrix of memory cells with sectors organized into columns, wherein each sector has a group of local word lines individually connected to a mai |
| 6504758 |
Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row d |
January 7, 2003 |
| Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row |
| 6493268 |
Circuit device for performing hierarchic row decoding in non-volatile memory devices |
December 10, 2002 |
| A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. Th |
| 6493260 |
Nonvolatile memory device, having parts with different access time, reliability, and capacity |
December 10, 2002 |
| The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a multilevel array, and a memory section containing cells that can be programmed with two levels, i.e., a bilevel array. The multilevel |
