| Patent Number |
Title Of Patent |
Date Issued |
| 7490276 |
Testing self-repairing memory of a device |
February 10, 2009 |
| Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. |
| 7007211 |
Testing self-repairing memory of a device |
February 28, 2006 |
| Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. |
| 6138230 |
Processor with multiple execution pipelines using pipe stage state information to control indepe |
October 24, 2000 |
| A microprocessor comprises a plurality of instruction pipelines having a plurality of stages for processing a stream of instructions, circuitry for simultaneously issuing instructions into two or more of the pipelines without regard to whether one of the simultaneously issued instructions |
| 5835967 |
Adjusting prefetch size based on source of prefetch address |
November 10, 1998 |
| A prefetch unit is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. Normally, the prefetch unit performs split prefetching by generating low and high prefetch addresses in a single clock, with the |
| 5835951 |
Branch processing unit with target cache read prioritization protocol for handling multiple hits |
November 10, 1998 |
| An up/dn read prioritization protocol is used to select between multiple hits in a set associative cache. Each set has associated with it an up/dn priority bit that controls read prioritization for multiple hits in the set--the up/dn bit designates either (i) up prioritization in which t |
| 5835949 |
Method of identifying and self-modifying code |
November 10, 1998 |
| A system and method of readily identifying and handling self-modifying variable length instructions in a pipelined processor is disclosed employing index tags associated with each stage of the execution pipeline wherein the index tags identify the cache line numbers in the instruction |
| 5784713 |
Address calculation logic including limit checking using carry out to flag limit violation |
July 21, 1998 |
| Address calculation logic in which an adder carry out flags a segment limit violation is used, in an exemplary embodiment, in a 486 type microprocessor. An effective address adder (24) and a three input adder (26) comprise limit checking logic. The three input adder receives on offse |
| 5771365 |
Condensed microaddress generation in a complex instruction set computer |
June 23, 1998 |
| A microarchitecture in a complex instruction computer system is disclosed employing a sparse microROM array and concatenation address circuitry for forming microaddress entry points, avoiding the need for a programmable logic array to translate instruction opcodes and avoiding duplicativ |
| 5740416 |
Branch processing unit with a far target cache accessed by indirection from the target cache |
April 14, 1998 |
| A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. In one embodiment, the BPU includes a target cache and a separate far target cache--the far target cache stores limits |
| 5732253 |
Branch processing unit with target cache storing history for predicted taken branches and histor |
March 24, 1998 |
| A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU implements a branch prediction scheme using a target cache and a separate history cache. The target cache |
| 5732243 |
Branch processing unit with target cache using low/high banking to support split prefetching |
March 24, 1998 |
| A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a target cache organized in banks to support split prefetching. Prefetch requests (addressing a p |
| 5706491 |
Branch processing unit with a return stack including repair using pointers from different pipe s |
January 6, 1998 |
| A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a return stack for call/returns, including return stack pointer repair in the case of the failure |
| 5692168 |
Prefetch buffer using flow control bit to identify changes of flow within the code stream |
November 25, 1997 |
| A prefetch unit includes flow control for controlling the transfer of instruction bytes from a prefetch buffer to a decoder where the prefetch buffer includes predicted change of flow instructions. Instruction bytes in the prefetch buffer are arranged in prefetch blocks--associated with |
| 5644741 |
Processor with single clock decode architecture employing single microROM |
July 1, 1997 |
| A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memor |
| 5337269 |
Carry skip adder with independent carry-in and carry skip paths |
August 9, 1994 |
| A carry skip adder uses independent paths for propagating a skip carry bit and a carry-in bit. Propagation of the carry-in bit is inhibited during a first portion of the clock cycle to prevent spurious carry-in signals from affecting the operation. During this period, other logic functio |
| 5294845 |
Data processor having an output terminal with selectable output impedances |
March 15, 1994 |
| A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled |
