| Patent Number |
Title Of Patent |
Date Issued |
| 5890201 |
Content addressable memory having memory cells storing don't care states for address translation |
March 30, 1999 |
| A method of accessing a content addressable memory storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state, is disclosed. The stored information is compared with a one bit signal. A match is indicated when the |
| 5784709 |
Translating buffer and method for translating addresses utilizing invalid and don't care states |
July 21, 1998 |
| A translation buffer and method for translating a virtual address to a physical address are disclosed. The translation buffer includes a plurality of storage locations, each including a tag store for storing a virtual page number and a data store for storing an associated physical pa |
| 5568415 |
Content addressable memory having a pair of memory cells storing don't care states for address t |
October 22, 1996 |
| A content addressable memory has a pair of single-bit memory cells together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state. Each of the memory cells has a pair of transistors. One of the transistors conne |
| 5325495 |
Reducing stall delay in pipelined computer system using queue between pipeline stages |
June 28, 1994 |
| A pipelined computer system employs a queue stage to receive the output of one pipeline stage when a stall occurs in the next stage or downstream of the next stage. This avoids stalling earlier stages of the pipeline. Subsequently, the pipeline advances through the queue, until a bubble |
| 4887232 |
Apparatus and method for performing a shift operation in a multiplier array circuit |
December 12, 1989 |
| In floating point operations, it is necessary to align the fractions of the floating point operands before addition or subtraction operations can be executed. This fraction alignment is performed by a shifting operation, typically using dedicated apparatus such as a barrel shifter. While |
| 4811272 |
Apparatus and method for an extended arithmetic logic unit for expediting selected floating poin |
March 7, 1989 |
| Apparatus and method for expediting the alignment of the fraction portion of operands in floating point operations. The alignment is performed in the arthmetic logic unit where the argument of the operand A exponent is subtracted from the argument of the operand B exponent. Because the r |
