| Patent Number |
Title Of Patent |
Date Issued |
| 7100020 |
Digital communications processor |
August 29, 2006 |
| An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management |
| 6449713 |
Implementation of a conditional move instruction in an out-of-order processor |
September 10, 2002 |
| A technique for handling a conditional move instruction in an out-of-order data processor. The technique involves detecting a conditional move instruction within an instruction stream, and generating multiple instructions according to the detected conditional move instruction. The te |
| 6195748 |
Apparatus for sampling instruction execution information in a processor pipeline |
February 27, 2001 |
| An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. E |
| 6163840 |
Method and apparatus for sampling multiple potentially concurrent instructions in a processor pi |
December 19, 2000 |
| An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A |
| 6081887 |
System for passing an index value with each prediction in forward direction to enable truth pred |
June 27, 2000 |
| A technique for predicting the result of a conditional branch instruction for use with a processor having instruction pipeline. A stored predictor is connected to the front end of the pipeline and is trained from a truth based predictor connected to the back end of the pipeline. The stor |
| 6000044 |
Apparatus for randomly sampling instructions in a processor pipeline |
December 7, 1999 |
| An apparatus is provided for sampling instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus includes a fetch unit for fetching instructions into a first stage of the pipeline. Certain randomly selected instructions are iden |
| 5933860 |
Multiprobe instruction cache with instruction-based probe hint generation and training whereby t |
August 3, 1999 |
| A computer system including an instruction cache (I-cache) having a plurality of banks for storing a subset of data from memory is shown to include a prediction mechanism for predicting which bank of the I-cache contains the required data. A prediction value, including a sequential p |
