| Patent Number |
Title Of Patent |
Date Issued |
| RE31473 |
System for fabrication of semiconductor bodies |
December 27, 1983 |
| A system and method is provided for forming semiconductor tear-drop shaped bodies having minimal grain boundaries. Semiconductor material is melted in a capillary tube at the top of a tower, and forced under gas pressure through a nozzle. Separate semiconductor bodies are formed. They ar |
| 7402514 |
Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant inte |
July 22, 2008 |
| An embodiment of the instant invention is a method of providing a connection between a first conductor and a second conductor wherein the first conductor is situated under the second conductor and separated by a first insulating layer, the method comprising the steps of: forming an o |
| 7323727 |
System with meshed power and signal buses on cell array |
January 29, 2008 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 7211842 |
System with meshed power and signal buses on cell array |
May 1, 2007 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 6967371 |
System with meshed power and signal buses on cell array |
November 22, 2005 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 6831317 |
System with meshed power and signal buses on cell array |
December 14, 2004 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 6815742 |
System with meshed power and signal buses on cell array |
November 9, 2004 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 6653676 |
Integrated circuit capacitor |
November 25, 2003 |
| The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a firs |
| 6559050 |
Process for high thermal stable contact formation in manufacturing sub-quarter-micron CMOS devic |
May 6, 2003 |
| A conducting plug/contact structure for use with integrated circuit includes a tungsten conducting plug formed in the via with a tungsten-silicon-nitride (WSi.sub.Y N.sub.Z) region providing the interface between the tungsten conducting plug and the substrate (silicon) layer. The int |
| 6528888 |
Integrated circuit and method |
March 4, 2003 |
| An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including |
| 6512257 |
System with meshed power and signal buses on cell array |
January 28, 2003 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 6461955 |
Yield improvement of dual damascene fabrication through oxide filling |
October 8, 2002 |
| A dual damascene process. After the via etch, a via protect layer (114) is deposited in the via (112). The via protect layer (114) comprises a material that has a dry etch rate at least equal to that of the IMD (108) and a wet etch rate that is approximately 100 times that of the IMD (10 |
| 6396088 |
System with meshed power and signal buses on cell array |
May 28, 2002 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 6294420 |
Integrated circuit capacitor |
September 25, 2001 |
| The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a firs |
| 6288925 |
System with meshed power and signal buses on cell array |
September 11, 2001 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 6261884 |
Method of fabricating and operating single polysilicon flash EEPROM with low positive programmin |
July 17, 2001 |
| A single polysilicon memory cell (10) provides a positive low programming and erase voltage together with a small cell size and includes P substrate (12) and P-well (14) formed within P substrate (12). NMOS transistor (16) is formed within P-well (14). N.sup.+ control gate (26) is formed |
| 6239479 |
Thermal neutron shielded integrated circuits |
May 29, 2001 |
| A thermal neutron shield (520) for integrated circuits (511-515) deters absorption of thermal neutrons by circuit constituents to form unstable isotopes with subsequent decay which generates bursts of charge which may upset of stored charge and create soft errors. The shielding may be ei |
| 6218311 |
Post-etch treatment of a semiconductor device |
April 17, 2001 |
| Post-etch treatment of an etch-damaged semiconductor device includes forming a protective cover (48, 148) over an oxidizable section (18, 118) of the semiconductor device. The protective cover (48, 148) is operable to at least inhibit oxidation of the oxidizable section (18, 118). While |
| 6115279 |
System with meshed power and signal buses on cell array |
September 5, 2000 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 6096597 |
Method for fabricating an integrated circuit structure |
August 1, 2000 |
| In one embodiment, the present invention provides a method of treating a dielectric layer 24. First, the dielectric layer is heated while being subjected to an O.sub.2 plasma. After that, the dielectric layer is heated while being subject to an ozone environment. This method can be usefu |
| 6069813 |
System with meshed power and signal buses on cell array |
May 30, 2000 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 6060354 |
In-situ doped rough polysilicon storage cell structure formed using gas phase nucleation |
May 9, 2000 |
| A method for forming a semiconductor memory device storage cell structure having an increased surface area. The storage cell structure has one or more rough polysilicon surfaces formed by depositing the polysilicon under conditions that result in gas phase dominant nucleation. |
| 6054732 |
Single polysilicon flash EEPROM with low positive programming and erasing voltage and small cell |
April 25, 2000 |
| A single polysilicon memory cell (10) provides a positive low programming and erase voltage together with a small cell size and includes P substrate (12) and P-well (14) formed within P substrate (12). NMOS transistor (16) is formed within P-well (14). N.sup.+ control gate (26) is formed |
| 5953242 |
System with meshed power and signal buses on cell array |
September 14, 1999 |
| A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The p |
| 5441902 |
Method for making channel stop structure for CMOS devices |
August 15, 1995 |
| In a semiconductor device having two N type regions separated by a P type region, a channel stop is needed to prevent shorting between the two N type regions. The channel stop of the invention has oxide isolators over the two N type regions and a P+ type diffusion lying between the oxide |
| 5352913 |
Dynamic memory storage capacitor having reduced gated diode leakage |
October 4, 1994 |
| A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed |
| 5252506 |
Method to eliminate gate filaments on field plate isolated devices |
October 12, 1993 |
| A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate |
| 5251168 |
Boundary cells for improving retention time in memory devices |
October 5, 1993 |
| By placing boundary cells within areas of discontinuity of a memory array, such as in word line strap areas, stress on edge cells of the memory array is reduced; the reduction of stress improves leakage characteristics and pause-refresh capabilities of edge cells. The boundary cells may |
| 5216265 |
Integrated circuit memory devices with high angle implant around top of trench to reduce gated d |
June 1, 1993 |
| A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at |
| 5202279 |
Poly sidewall process to reduce gated diode leakage |
April 13, 1993 |
| A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed |
| 4614835 |
Photovoltaic solar arrays using silicon microparticles |
September 30, 1986 |
| The disclosure relates to a photovoltaic solar array which is provided with a matrix having spherical photovoltaic diode particles embedded therein in an ordered array, the P-type region of each particle extending to one matrix surface and the N-type region of each particle extending to |
| 4430150 |
Production of single crystal semiconductors |
February 7, 1984 |
| Polycrystalline semiconductor material is treated to form a skin of a thermally stable substance and melted with the molten material retained by the film. Upon cooling, the material solidifies as single crystal and the skin is removed. |
| 4425408 |
Production of single crystal semiconductors |
January 10, 1984 |
| Polycrystalline semiconductor material is treated to form a skin of a thermally stable substance and melted with the molten material retained by the film. Upon cooling, the material solidifies as single crystal and the skin is removed. |
| 4413020 |
Device fabrication incorporating liquid assisted laser patterning of metallization |
November 1, 1983 |
| Laser patterning of metallization is done by transmitting laser energy through a liquid film directly in contact with the metallization to be patterned. When the metal is evaporated by the laser energy, the vapor is condensed immediately by the liquid film. This prevents redeposition of |
| 4322379 |
Fabrication process for semiconductor bodies |
March 30, 1982 |
| A system and method is provided for forming semiconductor tear-drop shaped bodies having minimal grain boundaries. Semiconductor material is melted in a capillary tube at the top of a tower, and forced under gas pressure through a nozzle. Separate semiconductor bodies are formed. They ar |
| 4188177 |
System for fabrication of semiconductor bodies |
February 12, 1980 |
| A system and method is provided for forming semiconductor tear-drop shaped bodies having minimal grain boundaries. Semiconductor material is melted in a capillary tube at the top of a tower, and forced under gas pressure through a nozzle. Separate semiconductor bodies are formed. They ar |
