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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Maxson; Mark Owen
Address:
Mantorville, MN
No. of patents:
40
Patents:












Patent Number Title Of Patent Date Issued
8174103 Enhanced architectural interconnect options enabled with flipped die on a multi-chip package May 8, 2012
A particular chip is designed having a first variant (front side connected chip) of the chip and a second variant (back side connected chip). The first variant of the chip is attached to a carrier. The second variant of the chip is attached to the carrier inverted relative to the fir
8108647 Digital data architecture employing redundant links in a daisy chain of component modules January 31, 2012
A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output li
8079134 Method of enhancing on-chip inductance structure utilizing silicon through via technology December 20, 2011
A method is provided that utilizes silicon through via technology, to build a Toroid into the chip with the addition of a layer of magnetic material such as Nickel above and below the T-coil stacked multi-ring structure. This allows the connection between the inner via and an array o
7954081 Implementing enhanced wiring capability for electronic laminate packages May 31, 2011
Structures and a computer program product are provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are
7945883 Apparatus, and computer program for implementing vertically coupled noise control through a mesh May 17, 2011
A method, apparatus and computer program product are provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package
7852103 Implementing at-speed Wafer Final Test (WFT) with complete chip coverage December 14, 2010
A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-
7844769 Computer system having an apportionable data bus and daisy chained memory chips November 30, 2010
A memory system having a data bus coupling a memory controller and a memory. The data bus has a number of data bus bits. The data bus is programmably apportioned to a first portion dedicated to transmitting data from the memory controller to the memory and a second portion dedicated
7675164 Method and structure for connecting, stacking, and cooling chips on a flexible carrier March 9, 2010
A heat sink apparatus having a plurality of chips attached to a first surface of a flexible carrier and a plurality of heat sink fins. One or more additional chips may be attached to a second surface of the flexible carrier. The flexible carrier has at least one complementary fold, the
7673093 Computer system having daisy chained memory chips March 2, 2010
A computer system having a memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and
7660942 Daisy chainable self timed memory chip February 9, 2010
A memory chip suitable for use in a daisy chain of memory chips. Timing of an array on the memory chip is dynamically determined by circuitry on the memory chip that tracks an access timing of the array. The memory chip is configured to receive an address/command word, determine if the
7660940 Carrier having daisy chain of self timed memory chips February 9, 2010
A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memor
7627711 Memory controller for daisy chained memory chips December 1, 2009
A memory controller configured to control a daisy chain of memory chips. The memory controller receives read and write requests from a processor, determines a daisy chain of memory chips that the request is directed to, determines which memory chip in the chain of memory chips the reques
7620763 Memory chip having an apportionable data bus November 17, 2009
A memory chip having a data bus having a plurality of bits. The number of bits is apportioned between a read portion and a write portion. The write portion is dedicated to receiving data that is to be written into an array on the memory chip; the read portion is dedicated to driving data
7617350 Carrier having daisy chained memory chips November 10, 2009
A carrier having at least one memory chip in a daisy chain of memory chips. A first carrier has at least a portion of an entire daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory
7577811 Memory controller for daisy chained self timed memory chips August 18, 2009
A memory controller for controlling a daisy chain of self timed memory chips. The memory controller has information as to how long each self timed memory chip in the daisy chain of memory chips takes to make a read access and a write access to an array on the self timed memory chip. The
7553696 Method for implementing component placement suspended within grid array packages for enhanced el June 30, 2009
A method and structure are provided for implementing component placement suspended within electrical pin grid array packages for enhanced electrical performance. A solder column grid array is coupled between a printed circuit board and a first level package. A component is connected
7546410 Self timed memory chip having an apportionable data bus June 9, 2009
A self timed memory chip having an apportionable data bus. Access timing to an array on the memory chip is dynamically determined by circuitry on the memory chip. A ring oscillator on the memory chip has a frequency that is indicative of how fast an array on the memory chip can be ac
7545664 Memory system having self timed daisy chained memory chips June 9, 2009
A memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory chips in the daisy chain of memory chips. Da
7490186 Memory system having an apportionable data bus and daisy chained memory chips February 10, 2009
A memory system having a memory controller and a daisy chain of memory chips. The memory controller is coupled to memory chips in the daisy chain of memory chips by an address/command bus chain. The memory controller is coupled to memory chips in the daisy chain of memory chips by a
7480201 Daisy chainable memory chip January 20, 2009
A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip. If not, the memory chip
7472368 Method for implementing vertically coupled noise control through a mesh plane in an electronic p December 30, 2008
A method is provided for implementing vertically coupled noise control through a mesh plane in an electronic package design. Electronic package physical design data are received. Instances of vertically coupled noise in the electronic package physical design data are identified. The
7472360 Method for implementing enhanced wiring capability for electronic laminate packages December 30, 2008
A method is provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified in
7402912 Method and power control structure for managing plurality of voltage islands July 22, 2008
A power control method and power control structures are provided for managing a plurality of voltage islands of a functional chip. The power control structure includes a supply control and partition chip positioned between a substrate carrier and a functional chip including a plurality
7345901 Computer system having daisy chained self timed memory chips March 18, 2008
A computer system having a memory system, the memory system having a memory controller and a memory. The memory comprises one or more daisy chains of self timed memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of the memory
7345900 Daisy chained memory system March 18, 2008
A memory system having a memory controller and a memory. The memory controller is coupled to a processor and to the memory. The memory comprises one or more daisy chains of memory chips. An address/command word is chained through a daisy chain of memory chips and is handled by one of
7342816 Daisy chainable memory chip March 11, 2008
A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip respondent to the add
7234017 Computer system architecture for a processor connected to a high speed bus transceiver June 19, 2007
A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a
7202685 Embedded probe-enabling socket with integral probe structures April 10, 2007
A method of testing and an embedded probe-enabling socket are provided for implementing debug and testing functions. The socket includes an integral probe structure enabling Top Side of the Module (TSM) signal probing. The socket includes a substrate with a topside including a plurality
7131084 Method, apparatus and computer program product for implementing automated detection excess aggre October 31, 2006
A method, apparatus and computer program product are provided for implementing automated detection of excess aggressor shape capacitance coupling in printed circuit board layouts. A PCB design file containing an electronic representation of a printed circuit board design is received.
7088200 Method and structure to control common mode impedance in fan-out regions August 8, 2006
A method and structure are provided to control common mode impedance in fan-out regions for printed circuit board applications. A differential pair transmission line includes a narrow signal trace portion in the fan-out region and a wider signal trace portion outside of the fan-out r
7088199 Method and stiffener-embedded waveguide structure for implementing enhanced data transfer August 8, 2006
A method and stiffener-embedded waveguide structure are provided for implementing enhanced data transfer for printed circuit board applications. At least one microwave channel is defined within a stiffener. The microwave channel provides a high frequency path for data transfers. Use
7074050 Socket assembly with incorporated memory structure July 11, 2006
A socket assembly with incorporated memory structure is provided. A chip carrier socket assembly includes dual stage clamping actuation. A first clamping actuation stage provides clamping force for ball grid array (BGA) contact pads and a second clamping actuation stage provides clam
7050871 Method and apparatus for implementing silicon wafer chip carrier passive devices May 23, 2006
Methods and apparatus are provided for implementing silicon wafer chip carrier passive devices including customized silicon capacitors and resistors mounted directly on a module or carrier package. A plurality of system design inputs is received for a package arrangement. A respective
7036710 Method and structures for implementing impedance-controlled coupled noise suppressor for differe May 2, 2006
A method and structures are provided for implementing an impedance-controlled coupled noise suppressor for a differential interface solder column array used to join a substrate to a circuit card. The impedance-controlled coupled noise suppressor structure includes a plurality of elon
7036709 Method and structure for implementing column attach coupled noise suppressor May 2, 2006
A method and structure are provided for implementing a column attach coupled noise suppressor for a solder column structure of the type used to join a substrate to a circuit card. The electrical noise suppressor structure includes a plurality of elongated through openings that are ar
7010768 Transmission line bounding models March 7, 2006
A method, apparatus, system, and signal-bearing medium that in an embodiment select a subset of transmission line models based on bounding electrical criteria. The bounding electrical criteria may include combinations of maximum and minimum values and in an embodiment may also includ
6998852 Method and apparatus for implementing direct attenuation measurement through embedded structure February 14, 2006
A method and apparatus are provided for implementing direct attenuation loss measurement in an electronic package. A sinusoidal voltage source signal of a selected frequency is coupled to an embedded transmission line test structure in the electronic package. Receive circuitry is cou
6987397 Method and probe structure for implementing a single probe location for multiple signals January 17, 2006
A method and a probe structure are provided for implementing multiple signals probing of a printed circuit board. A probe structure is formed on an outside surface of the printed circuit board. A resistor is electrically connected with an associated via with a signal to be monitored.
6956383 Method and apparatus for implementing automated electronic package transmission line characteris October 18, 2005
A method and apparatus are provided for implementing automated electronic package transmission line characteristic impedance verification. A sinusoidal voltage source is coupled to a transmission line test structure for generating a selected frequency. Impedance measuring circuitry is
6757175 Method and embedded bus bar structure for implementing power distribution June 29, 2004
A method and embedded bus bar structure are provided for implementing power distribution in an electronic system. A stiffener includes an embedded power bus bar structure for distributing power. The embedded power bus bar structure has a predefined pattern within a selected area of the










 
 
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