| Patent Number |
Title Of Patent |
Date Issued |
| 7554415 |
Microcomputer including a CR oscillator circuit |
June 30, 2009 |
| A microcomputer includes an oscillator for generating a clock signal having a frequency by using a CR circuit, a multiplier for outputting the clock signal having a multiplied frequency relative to the frequency generated by the oscillator based on data from an external source, a tem |
| 7519753 |
Communication system |
April 14, 2009 |
| A communication system includes a master control unit, a plurality of slave control units, and buses connecting the master control unit and the slave control units for the asynchronous communication. When the master control unit starts the communication, each slave control unit transmits |
| 7467294 |
Microcomputer with mode decoder operable upon receipt of either power-on or external reset signa |
December 16, 2008 |
| A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder deco |
| 7444529 |
Microcomputer having rewritable nonvolatile memory |
October 28, 2008 |
| A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or inter |
| 7421384 |
Semiconductor integrated circuit device and microcomputer development supporting device |
September 2, 2008 |
| During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits in the chip. For mo |
| 7356719 |
Microcomputer |
April 8, 2008 |
| In an EEPROM of a microcomputer, data is stored for determining a communication rate CMR for fixing the data transmission time of one frame managed by a communication circuit on the basis of an oscillation output characteristic of a CR oscillating circuit that varies in accordance with |
| 7216250 |
Clock control circuit for correcting frequency of second clock signal based on first clock signa |
May 8, 2007 |
| The present invention relates to a clock control circuit apparatus including a first oscillation circuit for generating a first clock signal and a second oscillation circuit for generating a second clock signal and capable of, when the two clock signals are put to use, improving the |
| 7149915 |
Microcomputer using a shared counter |
December 12, 2006 |
| In a microcomputer, a watch-dog timer and a sleep control timer share a counter in their signal generating circuits. In a normal operation mode, an AND gate is in a signal passing state and a reset signal RST can be outputted. In a sleep mode, another AND gate is in a signal passing stat |
