| Patent Number |
Title Of Patent |
Date Issued |
| RE38679 |
Data processor and method of processing data |
December 28, 2004 |
| A second decoder (114) of an instruction decode unit (119) decodes an operation code for a multiply-add operation, and a second operation unit (117) receives two data stored in a register file (115) to perform the multiply-add operation. In parallel with the operations of the second |
| 7010677 |
Data processor speeding up repeat processing by inhibiting remaining instructions after a break |
March 7, 2006 |
| A comparator 172 compares the value held in an RPT_B register 171 with the address of the instruction which is held in an IA register 181 and is to be fetched next, and outputs coincidence information indicating whether these value coincide with each other. Based on the coincidence i |
| 6925548 |
Data processor assigning the same operation code to multiple operations |
August 2, 2005 |
| A data processor can assign a greater number of operations to instruction codes with shorter length, thereby implementing high performance, high code efficiency and low cost data processor. The data processor is a VLIW (Very Long Instruction Word) system that can execute a plurality of |
| 6484253 |
Data processor |
November 19, 2002 |
| The present invention relates to a data processor, and particularly in a data processor performing condition execution on the basis of flag information, aims at obtaining a data processor having excellent code efficiency, which can reduce branch penalty. In order to attain the aforem |
| 6178492 |
Data processor capable of executing two instructions having operand interference at high speed i |
January 23, 2001 |
| A data processor comprises an instruction decoding unit having two decoders decoding respective instructions of an instruction group consisting of a plurality of instructions including a first instruction and a second instruction succeeding the first instruction, and a judging unit judgi |
| 6112289 |
Data processor |
August 29, 2000 |
| A data processor comprises an instruction decoding unit having two decoders decoding respective instructions of an instruction group consisting of a plurality of instructions including a first instruction and a second instruction succeeding the first instruction, and a judging unit judgi |
| 5924114 |
Circular buffer with two different step sizes |
July 13, 1999 |
| A control unit (112) makes different judgments on the end address, depending on whether 1-word access or 2-word access, based on a post-update signal (507) and a 2-word access signal (508) which are internally generated and a coincidence signal (511) on the high-order 14 bits and ano |
| 5901301 |
Data processor and method of processing data |
May 4, 1999 |
| A second decoder (114) of an instruction decode unit (119) decodes an operation code for a multiply-add operation, and a second operation unit (117) receives two data stored in a register file (115) to perform the multiply-add operation. In parallel with the operations of the second |
