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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Matsuda; Yoshio
Address:
Hyogo, JP
No. of patents:
43
Patents:












Patent Number Title Of Patent Date Issued
7725847 Wiring design support apparatus for bond wire of semiconductor devices May 25, 2010
A design support apparatus supports wiring design for bond wires that connect a semiconductor chip and an interposer. The design support apparatus includes a creating unit that creates simulated design data simulating occurrence of fluctuation in an arrangement position of a semicond
6802048 Design support apparatus and method for designing semiconductor packages October 5, 2004
A design support apparatus, when designing multichip packages, verifies connections between a semiconductor chip and leads of a lead frame. Distances between two wires or distances between the wires and the other components are calculated using three-dimensional drawing data (CAD data)
5509132 Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and ope April 16, 1996
A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each
5504713 Semiconductor memory device with redundancy circuit April 2, 1996
A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a
5461589 Bit line structure for semiconductor memory device with bank separation at cross-over regions October 24, 1995
A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the resp
5416734 Bit line structure for semiconductor memory device May 16, 1995
A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the resp
5412380 Electronic crosspoint switching device operating at a high signal transmission rate May 2, 1995
A crosspoint LSI adapted to an exchanger in ISDN, for transmission of asynchronous transfer mode (ATM) cells in communication is provided. The crosspoint switching LSI includes many unit switch cells arranged in rows and columns. When a unit switch cell is turned on, the unit switch cell
5371714 Method and apparatus for driving word line in block access memory December 6, 1994
In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifi
5353427 Semiconductor memory device for simple cache system with selective coupling of bit line pairs October 4, 1994
A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory
5289417 Semiconductor memory device with redundancy circuit February 22, 1994
A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a
5280443 Bit line structure for semiconductor memory device January 18, 1994
A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the
5267214 Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory de November 30, 1993
A dynamic random access memory amplifier arrangement includes a sense amplifier band shared between two different memory blocks. In this memory, only sense amplifiers related to a selected memory block are activated. The memory comprises a circuit for boosting a control signal voltage to
5250458 Method for manufacturing semiconductor memory device having stacked memory capacitors October 5, 1993
A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner
5226147 Semiconductor memory device for simple cache system July 6, 1993
A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory
5222047 Method and apparatus for driving word line in block access memory June 22, 1993
In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timing of activating the sense amplifi
5214601 Bit line structure for semiconductor memory device including cross-points and multiple interconn May 25, 1993
A semiconductor memory device of folded bit line structure includes a cross portion in at least one portion of each bit line pair so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines. Preferably, the respective b
5185744 Semiconductor memory device with test circuit February 9, 1993
A semiconductor memory device comprises a plurality of memory array blocks (B1 to B4). In each of the plurality of memory array blocks (B1 to B4), a line mode test is performed. Results of the line mode tests performed in the memory array blocks (B1 to B4) are outputted to corresponding
5184327 Semiconductor memory device having on-chip test circuit and method for testing the same February 2, 1993
In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15 20). The output line (L) is provided with plu
5179687 Semiconductor memory device containing a cache and an operation method thereof January 12, 1993
A DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, a plurality of data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive
5136543 Data descrambling in semiconductor memory device August 4, 1992
A semiconductor memory device comprises a plurality of bit line pairs and an input/output line pair. Each bit line pair comprises first and second bit lines supplied with complementary data, and the input/output line pair comprises first and second input/output lines supplied with comple
5103426 Decoding circuit and method for functional block selection April 7, 1992
An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to
5088063 Semiconductor memory device having on-chip test circuit February 11, 1992
In a memory cell array of a semiconductor memory device, a plurality of detection circuits (14, 15, 20) are provided in correspondence with a plurality of columns. An output line (L) is provided in common to the detection circuits (14, 15, 20). The output line (L) is provided with pl
5060230 On chip semiconductor memory arbitrary pattern, parallel test apparatus and method October 22, 1991
An apparatus for parallel testing of a semiconductor memory with arbitrary data patterns and capable of being integrated on the memory chip. The semiconductor memory test device in a preferred embodiment is compatible with hierarchical data bus lines including an input/output line pair (
5030586 Method for manufacturing semiconductor memory device having improved resistance to .alpha. parti July 9, 1991
In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type
5022007 Test signal generator for semiconductor integrated circuit memory and testing method thereof June 4, 1991
A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored therein. When a transfer (67) is
5014241 Dynamic semiconductor memory device having reduced soft error rate May 7, 1991
Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line.
5012447 Bit line structure for a dynamic type semiconductor memory device April 30, 1991
Each of the bit lines constituting each of a plurality of bit line pairs included in a portion of a memory cell array comprises even-numbered intersecting portions. At the intersecting portion, the materials of respective bit lines are different from each other. The bit lines are for
4980310 Method of making a trench dram cell December 25, 1990
A dynamic semiconductor memory device comprising a substrate having one trench including two capacitors for memory cell capacitances of two bits, and two elements such as transistors for reading, writing, and storing information represented by charge, arranged symmetrically at the centra
4977542 Dynamic semiconductor memory device of a twisted bit line system having improved reliability of December 11, 1990
An arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines. Two dummy word lines maintained at a predetermined potential are formed at a twisted portion of a pair of bit lines. Dummy cells are
4972380 Decoding circuit for functional block November 20, 1990
An address decoding circuit for a functional block comprises branch portions serially connected with each other, in which a selecting signal is outputted on one of two output portions in accordance with the first bit information of an address signal when a selecting signal is applied to
4953164 Cache memory system having error correcting circuit August 28, 1990
There are provided a first memory cell array and a second memory cell array. The first memory cell array comprises a dynamic RAM and the second memory cell array comprises a static RAM. In addition, the second memory cell array has smaller capacity than that of the first memory cell arra
4926385 Semiconductor memory device with cache memory addressable by block within each column May 15, 1990
A semiconductor memory includes a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines. A plurality of memory cells are arranged at intersections of the bit lines and the word lines, respectively. Word line selecting cir
4918692 Automated error detection for multiple block memory array chip and correction thereof April 17, 1990
A semiconductor memory device comprises a plurality of memory cell array blocks. An address changing system is provided in each memory cell array block. The same address signal is applied to these address changing systems. Each address changing system comprises a plurality of linking
4914632 Semiconductor devices having redundancy circuitry and operating method therefor April 3, 1990
A plurality of word drivers are provided corresponding to a plurality of word lines. A switch band is provided between the plurality of word drivers and a plurality of row decoders. Each row decoder is connected to four word drivers through the switch band. The state of connection betwee
4914630 Refresh arrangement in a block divided memory including a plurality of shift registers April 3, 1990
In a block access memory, the memory cell array is divided into a plurality of blocks, one word line is selected based on the external address and the access to the memory cells connected thereto is carried out in one block and, simultaneously, one word line is selected based on the inte
4890261 Variable word length circuit of semiconductor memory December 26, 1989
A word length variable circuit of a semiconductor memory comprises a shift register provided corresponding to rows or columns of a memory cell array. The input of the first stage of the shift register is connected to the output of the last stage and regions of the shift register is group
4887136 Semiconductor memory device and the method for manufacturing the same December 12, 1989
A dynamic semiconductor memory device comprising a substrate having one trench including two capacitors for memory cell capacitances of two bits, and two elements such as transistors for reading, writing, and storing information represented by charge, arranged symmetrically at the centra
4855953 Semiconductor memory device having stacked memory capacitors and method for manufacturing the sa August 8, 1989
A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner
4833653 Dynamic random access memory having selectively activated subarrays May 23, 1989
A DRAM of a partially activating system, in which, in an active cycle, sense amplifiers (91a, 91b) are inactivated and the potential on each pair of bit lines (BLA1, BLA1, BLA2, BLA2) is equalized early in the active cycle only for a subarray to be accessed while the potential is not
4833645 Semiconductor memory device having improved resistance to alpha particle induced soft errors May 23, 1989
In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type
4833518 Semiconductor memory device having improved interconnection structure of memory cell array May 23, 1989
A memory cell array is divided into two groups, one bit line of a pair of bit lines is connected to corresponding memory cells in the first group of the memory cell array, and the other bit line thereof is connected to corresponding memory cells in the second group of the memory cell arr
4797001 Substrate bias generator for use in dynamic random access memory January 10, 1989
The invention relates to a substrate bias generator for use in dynamic random access memory, and in which either a plurality of transistors for rectification are disposed between a coupling capacitor and a substrate potential electrode or a threshold voltage of a transistor for recti
4788457 CMOS row decoder circuit for use in row and column addressing November 29, 1988
A CMOS row decoder circuit in which a row decoder for selecting a single word line from a memory cell array and a column decoder for selecting a single bit line can use in common an internal address signal transmission line. The row decoder circuit comprises a series of MOSFETs of a firs










 
 
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