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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Mathew; Suraj
Address:
Boise, ID
No. of patents:
12
Patents:












Patent Number Title Of Patent Date Issued
8158471 Capacitorless DRAM on bulk silicon April 17, 2012
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon subst
7897460 Methods of forming recessed access devices associated with semiconductor constructions March 1, 2011
The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access de
7858458 CMOS fabrication December 28, 2010
A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMO
7829399 Capacitorless DRAM on bulk silicon November 9, 2010
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon subst
7601591 Method of manufacturing sidewall spacers on a memory device, and device comprising same October 13, 2009
The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array
7538389 Capacitorless DRAM on bulk silicon May 26, 2009
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon subst
7517744 Capacitorless DRAM on bulk silicon April 14, 2009
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon subst
7462534 Methods of forming memory circuitry December 9, 2008
The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The
7459742 Method of manufacturing sidewall spacers on a memory device, and device comprising same December 2, 2008
The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array
7384849 Methods of forming recessed access devices associated with semiconductor constructions June 10, 2008
The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access de
7341906 Method of manufacturing sidewall spacers on a memory device, and device comprising same March 11, 2008
The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array
7332388 Method to simultaneously form both fully silicided and partially silicided dual work function tr February 19, 2008
A method for forming transistor gates having two different work functions comprises forming a first polysilicon layer which may be doped with n-type dopants. The first polysilicon layer comprises an inhibitor material at select locations which retards silicide formation. A second pol










 
 
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