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Inventor: Masenas, Jr.; Charles J.
Address: Jericho, VT
No. of patents: 3
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 4555776 |
Voltage balancing circuit for memory systems |
November 26, 1985 |
| A voltage balancing circuit, particularly suitable for bipolar memory arrays producing small signals, is provided which includes first and second conductive lines, a point of reference potential, a first device disposed between the first conductive line and the point of reference pot |
| 4404662 |
Method and circuit for accessing an integrated semiconductor memory |
September 13, 1983 |
| A memory system is provided having an array of cells, each of which may include first and second cross-coupled inverting NPN transistors and first and second PNP transistors for injecting charge into the first and second inverting transistors. A first bit/sense line of a bit/sense line p |
| 4376252 |
Bootstrapped driver circuit |
March 8, 1983 |
| A driver circuit charges a capacitive load to a voltage substantially equal to the voltage or potential of the power supply of the circuit by first charging the capacitive load with current flowing through a drive transistor under the control of the power supply potential and, therea |
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