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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Mansfield; Scott M.
Address:
Hopewell Junction, NY
No. of patents:
24
Patents:












Patent Number Title Of Patent Date Issued
8214770 Multilayer OPC for design aware manufacturing July 3, 2012
A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention
8174681 Calibration of lithographic process models May 8, 2012
A method is provided for calibrating a model of a lithographic process that includes defining a parameter space of lithographic model parameters that are expected in an integrated circuit layout. The parameter space is defined according to bin values of a lithographic model parameter tha
8166423 Photomask design verification April 24, 2012
Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing p
8161422 Fast and accurate method to simulate intermediate range flare effects April 17, 2012
A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more particularly for simulating intermediate range flare effects. For a region of influence (ROI) from first ROI1 of about 5.lamda./NA to
8108804 Short path customized mask correction January 31, 2012
Embodiments of the present invention provide a method of performing photo-mask correction. The method includes identifying a hot-spot in a photo-mask that violates one or more predefined rules; creating a window area in the photo-mask that surrounds the hot spot; categorizing the win
8039203 Integrated circuits and methods of design and manufacture thereof October 18, 2011
Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the
7945869 Mask and method for patterning a semiconductor wafer May 17, 2011
A method for generating a mask pattern is provided. A target lithographic pattern comprising a plurality of first geometric regions is provided, wherein the regions between the plurality of first geometric regions comprise first spaces. The target lithographic pattern is transformed,
7895547 Test pattern based process model calibration February 22, 2011
Embodiments of the present invention provide a method for performing lumped-process model calibration. The method includes creating a plurality of sub-process models for a set of sub-processes; creating a lumped-process-model incorporating said set of sub-processes; calculating a fir
7765021 Method to check model accuracy during wafer patterning simulation July 27, 2010
A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-w
7650587 Local coloring for hierarchical OPC January 19, 2010
A method for designing a mask for fabricating an integrated circuit is provided wherein a mask layout that requires coloring, such as for alternating phase shift, double-exposure and double-exposure-etch masks, is organized into uncolored hierarchical design units. Prior to modificat
7642020 Method for separating optical and resist effects in process models January 5, 2010
A methodology to improve the through-process model calibration accuracy of a semiconductor manufacturing process using lithographic methods by setting the correct defocus and image plane position in a patterning process model build. Separations of the optical model and the photoresist
7607114 Designer's intent tolerance bands for proximity correction and checking October 20, 2009
A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the desig
7565633 Verifying mask layout printability using simulation with adjustable accuracy July 21, 2009
A method, system and computer program product for verifying printability of a mask layout for a photolithographic process are disclosed. A simulation of the photolithographic process for the designed mask layout is simulated using a simplified version of the mask layout with a lower
7503028 Multilayer OPC for design aware manufacturing March 10, 2009
A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention
7350183 Method for improving optical proximity correction March 25, 2008
A method for performing model based optical proximity correction (MBOPC) and a system for performing MBOPC is described, wherein the process model is decomposed into a constant process model term and a pattern dependent portion. The desired wafer target is modified by the constant proces
7343582 Optical proximity correction using progressively smoothed mask shapes March 11, 2008
A method, program product and system is disclosed for performing optical proximity correction (OPC) wherein mask shapes are fragmented based on the effective image processing influence of neighboring shapes on the shape to be fragmented. Neighboring shapes are smoothed prior to deter
7266798 Designer's intent tolerance bands for proximity correction and checking September 4, 2007
A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the desig
7261981 System and method of smoothing mask shapes for improved placement of sub-resolution assist featu August 28, 2007
A method is disclosed for providing associated shapes of an optical lithography mask in relation to predetermined main shapes of the mask. The method includes generating simplified layout patterns from the predetermined main shapes of the mask. Such layout patterns are generated by e
6541166 Method and apparatus for lithographically printing tightly nested and isolated device features u April 1, 2003
The present invention relates generally to a method for lithographically printing a mask pattern on a substrate, in particular a semiconductor substrate, wherein the mask pattern includes features with diverse pitches. These features may include device features such as vias or contac
6421820 Semiconductor device fabrication using a photomask with assist features July 16, 2002
A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method (see e.g., FIG. 4A) based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the
6413683 Method for incorporating sub resolution assist features in a photomask layout July 2, 2002
A method for developing a photomask layout by which an electrical circuit is imaged that includes introducing sub resolution assist features into a photomask layout by (1) sorting selected details of the main electrical circuit undergoing enhancement according to a predetermined order of
6346979 Process and apparatus to adjust exposure dose in lithography systems February 12, 2002
A process and apparatus for dynamically adjusting the exposure dose on a photosensitive coating at a localized area within an exposure field in a step-and-scan lithography system. The process and apparatus form a pattern on a photosensitive substrate, such as used in the integrated circu
5932377 Exact transmission balanced alternating phase-shifting mask for photolithography August 3, 1999
A two-step method for eliminating transmission errors in alternating phase-shifting masks is described. Initially, the design data is selectively biased to provide a coarse reduction in the inherent transmission error between features of different phase, size, shape, and/or location.
5757842 Method and apparatus for compensating thermal lensing effects in a laser cavity May 26, 1998
In a laser cavity having an optical axis, a laser medium for forming a laser beam, the laser medium having a central axis off-set from the optical axis, the laser medium exhibiting focusing characteristics that vary with changes in optical power pumped into the laser medium, at least










 
 
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