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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Mandelman; Jack A.
Address:
Stormville, NY
No. of patents:
236
Patents:


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Patent Number Title Of Patent Date Issued
7226816 Method of forming connection and anti-fuse in layered substrate such as SOI June 5, 2007
An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulato
7190042 Self-aligned STI for narrow trenches March 13, 2007
A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portion
7087948 Forming electronic structures having dual dielectric thicknesses and the structure so formed August 8, 2006
A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.
7026202 Inverse-T gate structure using damascene processing April 11, 2006
A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be diff
7009258 Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ d March 7, 2006
The present invention provides improved controllability of the lateral etch encroachment of silicon under the spacer, in light of the fact that the exemplary method, in accordance with the present invention, comprises the step of implanting neutral ions such as Ge or Ar into the sour
6972220 Structures and methods of anti-fuse formation in SOI December 6, 2005
An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulato
6911687 Buried bit line-field isolation defined active semiconductor areas June 28, 2005
Active areas of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines on two sides and by conductors separated from the semiconductor substrate by electrically insulating layers on two other sides. The conductors are electrically bi
6897107 Method for forming TTO nitride liner for improved collar protection and TTO reliability May 24, 2005
A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this line
6872620 Trench capacitors with reduced polysilicon stress March 29, 2005
A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below
6869846 Forming electronic structures having dual dielectric thicknesses and the structure so formed March 22, 2005
A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.
6833305 Vertical DRAM punchthrough stop self-aligned to storage trench December 21, 2004
A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench sto
6818528 Method for multi-depth trench isolation November 16, 2004
A method for forming multi-depth apertures in a substrate is provided. The method includes first providing a pad stack atop a surface of a substrate having regions for forming apertures therein, the pad stack includes at least a top patterned masking layer. Next, at least one of the regi
6815749 Backside buried strap for SOI DRAM trench capacitor November 9, 2004
In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trench and undercutting the insulating
6809372 Flash memory structure using sidewall floating gate October 26, 2004
A flash memory and a method of forming a flash memory, includes forming a polysilicon wordline on a substrate, the wordline having first and second sidewalls, the first sidewall being tapered, with respect to a surface of the substrate, to have a slope angle and the second sidewall havin
6809368 TTO nitride liner for improved collar protection and TTO reliability October 26, 2004
A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this line
6808981 Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned S October 26, 2004
A memory cell containing double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation, STI, regions that are self-aligned to the wordlines and bitlines of the cell are provided. The inventive memory cell substan
6790722 Logic SOI structure, process and application for vertical bipolar transistor September 14, 2004
A method and structure for forming an emitter in a vertical bipolar transistor includes providing a substrate having a collector layer and a base layer over the collector layer, forming a patterning mask over the collector layer, and filling openings in the mask with emitter material in
6777737 Vertical DRAM punchthrough stop self-aligned to storage trench August 17, 2004
A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench sto
6777733 Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays August 17, 2004
Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in forming the memory structure, dec
6767789 Method for interconnection between transfer devices and storage capacitors in memory cells and d July 27, 2004
The preferred embodiment of the present invention provides unique structure for connecting between a storage capacitor and a transfer device in a memory cell and a method for fabricating the same. The preferred embodiment of the present invention forms a capacitor structure having a
6762447 Field-shield-trench isolation for gigabit DRAMs July 13, 2004
A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower porti
6759291 Self-aligned near surface strap for high density trench DRAMS July 6, 2004
A method and structure for a dynamic random access memory device comprising a storage trench, a storage conductor within the storage trench, a lip strap connected to the storage conductor, and a control device electrically connected to the storage conductor through the lip strap. The
6740920 Vertical MOSFET with horizontally graded channel doping May 25, 2004
Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau havi
6734109 Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ d May 11, 2004
The present invention provides improved controllability of the lateral etch encroachment of silicon under the spacer, in light of the fact that the exemplary method, in accordance with the present invention, comprises the step of implanting neutral ions such as Ge or Ar into the source/d
6734056 Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell May 11, 2004
A 6F.sup.2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gated vertical MOSFET having exposed gate
6727539 Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect April 27, 2004
A structure and process for fabricating embedded vertical DRAM cells includes fabricating vertical MOSFET DRAM cells with silicided polysilicon layers in the array regions, the landing pad and/or interconnect structures, the support source and drain regions and/or the gate stack. The
6724088 Quantum conductive barrier for contact to shallow diffusion region April 20, 2004
Structures such as source/drain contacts of improved reliability are enabled by the creation and use of quantum conductive barrier layers at the interface between the electrical contact and the shallow diffusion source/drain region. The quantum conductive layers are preferably nitrides
6724029 Twin-cell flash memory structure and method April 20, 2004
A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disp
6720630 Structure and method for MOSFET with metallic gate electrode April 13, 2004
A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation process is provided. A semiconductor structure formed by the inventive method is also provi
6720602 Dynamic random access memory (DRAM) cell with folded bitline vertical transistor and method of p April 13, 2004
A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating
6693041 Self-aligned STI for narrow trenches February 17, 2004
A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portion
6674139 Inverse T-gate structure using damascene processing January 6, 2004
A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be differen
6674134 Structure and method for dual gate oxidation for CMOS technology January 6, 2004
The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device re
6656807 Grooved planar DRAM transfer device using buried pocket December 2, 2003
A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that
6653678 Reduction of polysilicon stress in trench capacitors November 25, 2003
A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below
6646949 Word line driver for dynamic random access memories November 11, 2003
A word line for a row of memory elements of a dynamic random access memory. A first transistor is connected to a source of negative potential and to the word line for switching the word line to a source of negative potential in response to a decoder signal. A diode is additionally co
6642566 Asymmetric inside spacer for vertical transistor November 4, 2003
A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wider connection between the wo
6635543 SOI hybrid structure with selective epitaxial growth of silicon October 21, 2003
A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon l
6635525 Method of making backside buried strap for SOI DRAM trench capacitor October 21, 2003
In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trench and undercutting the insulating
6632741 Self-trimming method on looped patterns October 14, 2003
A method of self-trimming pattern, includes forming a pattern containing a plurality of regular or irregular features within a first material deposited on a substrate, depositing a conformal layer of second material, and etching the second material to form spacers of the second material
6630379 Method of manufacturing 6F2 trench capacitor DRAM cell having vertical MOSFET and 3F bitline pit October 7, 2003
A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side w
6617702 Semiconductor device utilizing alignment marks for globally aligning the front and back sides of September 9, 2003
The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one
6614074 Grooved planar DRAM transfer device using buried pocket September 2, 2003
A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that
6613615 Pair of FETs including a shared SOI body contact and the method of forming the FETs September 2, 2003
A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is
6596592 Structures and methods of anti-fuse formation in SOI July 22, 2003
An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulato
6590259 Semiconductor device of an embedded DRAM on SOI substrate July 8, 2003
A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator ("SOI") regions and where buried, doped
6580136 Method for delineation of eDRAM support device notched gate June 17, 2003
A complementary metal oxide semiconductor integrated circuit containing a notched gate in the support device region as well as a method of forming the same are provided. The method of the present invention includes the steps of (a) forming a gate stack on a surface of a substrate, the ga
6576945 Structure and method for a compact trench-capacitor DRAM cell with body contact June 10, 2003
A compact DRAM cell array that substantially minimizes floating-body effects and device-to-device interactions is disclosed. The compact DRAM cell array includes a plurality of annular memory cells that are arranged in rows and columns. Each annular memory cell includes a vertical MOSFET
6573585 Electrically blowable fuse with reduced cross-sectional area June 3, 2003
A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a
6573561 Vertical MOSFET with asymmetrically graded channel doping June 3, 2003
Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold i
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