| Patent Number |
Title Of Patent |
Date Issued |
| 7590899 |
Processor memory array having memory macros for relocatable store protect keys |
September 15, 2009 |
| A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and sec |
| 7577795 |
Disowning cache entries on aging out of the entry |
August 18, 2009 |
| Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the main memory. For a system with shared L2 cache(s) between the processor(s) and the main m |
| 7523267 |
Method for ensuring fairness among requests within a multi-node computer system |
April 21, 2009 |
| A method to use of dual valid bit sets including a regular bit set and alternate valid bits set which prevents new requests to a given cache line from entering a multi-nodal computer systems' nest system until all requests to the given cache line have been completed successfully. By |
| 7475193 |
Separate data and coherency cache directories in a shared cache in a multiprocessor system |
January 6, 2009 |
| A dual system shared cache directory structure for a cache memory performs the role of an inclusive shared system cache, i.e., data, and system control, i.e., coherency. The system includes two separate system cache directories in the shared system cache. The two separate cache direc |
| 7379418 |
Method for ensuring system serialization (quiesce) in a multi-processor environment |
May 27, 2008 |
| A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies between nodes are |
| 7111130 |
Coherency management for a "switchless" distributed shared memory computer system |
September 19, 2006 |
| A shared memory symmetrical processing system including a plurality of nodes each having a system control element for routing internodal communications. A first ring and a second ring interconnect the plurality of nodes, wherein data in said first ring flows in opposite directions wi |
| 7085898 |
Coherency management for a "switchless" distributed shared memory computer system |
August 1, 2006 |
| An apparatus and method is disclosed to manage storage coherency in a symmetric multiprocessing environment having a plurality of nodes, each of which contain a multitude of processors, I/O adapters, main memory and a system controller comprising an integrated switch with a top level |
| 7085897 |
Memory management for a symmetric multiprocessor computer system |
August 1, 2006 |
| A modular multiprocessor computer system having a plurality of nodes each being in communication with each other via communication links. The plurality of nodes each have local memory and local cache accessible by the other nodes. The plurality of nodes each also having a cache direc |
| 7069362 |
Topology for shared memory computer system |
June 27, 2006 |
| A dual ring topology for multiprocessing computer systems. The dual ring topology interconnects multiple building blocks (nodes) to each other, each node comprising processing elements, memory and IO devices. The topology allows for the dual rings to be temporarily transformed into a |
| 6988173 |
Bus protocol for a switchless distributed shared memory computer system |
January 17, 2006 |
| A bus protocol is disclosed for a symmetric multiprocessing computer system consisting of a plurality of nodes, each of which contains a multitude of processors, I/O devices, main memory and a system controller comprising an integrated switch with a top level cache. The nodes are int |
| 6738872 |
Clustered computer system with deadlock avoidance |
May 18, 2004 |
| A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces between cluster nodes of the symmetric multiprocessor system with a local interface and an |
| 6738871 |
Method for deadlock avoidance in a cluster environment |
May 18, 2004 |
| A remote resource management system for managing resources in a symmetrical multiprocessing environment having a plurality of clusters of symmetric multiprocessors each of which provides interfaces between cluster nodes of the symmetric multiprocessor system with a local interface and an |
| 6738870 |
High speed remote storage controller |
May 18, 2004 |
| A high speed remote storage controller system for a computer system has cluster nodes of symmetric multiprocessors. A plurality of clusters of symmetric multiprocessors each of has a plurality of processors, a shared cache memory, a plurality of I/O adapters and a main memory accessible |
| 6654925 |
Method to determine retries for parallel ECC correction in a pipeline |
November 25, 2003 |
| Disclosed is an apparatus and means for searching a cache directory with full ECC support without the latency of the ECC logic on every directory search. The apparatus allows for bypassing the ECC logic in an attempt to search the directory. When a correctable error occurs which causes t |
| 6516393 |
Dynamic serialization of memory access in a multi-processor system |
February 4, 2003 |
| A method for resolving address contention and prioritization of access to resources within a shared memory system includes dynamically creating ordered lists of requests for each contested resource. A new request is added to the lists only after a conflict is recognized. Since the resour |
| 6219758 |
False exception for cancelled delayed requests |
April 17, 2001 |
| A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for |
| 6163857 |
Computer system UE recovery logic |
December 19, 2000 |
| A computer system having central processors (CPs), an associated L2 cache, and processor memory arrays (PMAs), is provided with store logic and and fetch logic used to detect and correct data errors and to write the resulting data the associated cache. The store logic and and fetch logic |
| 6151655 |
Computer system deadlock request resolution using timed pulses |
November 21, 2000 |
| Disclosed is a hardware mechanism for detecting and avoiding potential deadlocks among requestors in a multiprocessor system, consisting of a plurality of CP's and I/O adapters connected to one or more shared storage controllers (SC's). Requests to each storage controller originate from |
| 6119219 |
System serialization with early release of individual processor |
September 12, 2000 |
| A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled |
| 6079013 |
Multiprocessor serialization with early release of processors |
June 20, 2000 |
| A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled |
| 6073182 |
Method of resolving deadlocks between competing requests in a multiprocessor using global hang p |
June 6, 2000 |
| A method using a global hang pulse logic mechanism detects and resolves deadlocks among requesters to the storage controller of a symmetric multiprocessor system in which multiple central processors and I/O adapters are connected to one or more shared storage controllers. Deadlocks m |
| 6038651 |
SMP clusters with remote resource managers for distributing work to other clusters while reducin |
March 14, 2000 |
| A remote resource management system for managing resources in a symmetrical multiprocessing comprising a plurality of clusters of symmetric multiprocessors having interfaces between cluster nodes of the symmetric multiprocessor system. Each cluster of the system has a local interface |
| 5752264 |
Computer architecture incorporating processor clusters and hierarchical cache memories |
May 12, 1998 |
| A hierarchical cache architecture that reduces traffic on a main memory bus while overcoming the disadvantages of prior systems. The architecture includes a plurality of level one caches that are of the store through type, each level one cache is associated with a processor and may be |
| 5564062 |
Resource arbitration system with resource checking and lockout avoidance |
October 8, 1996 |
| A resource arbitration system is provided implementing a modified round robin priority selection logic including resource checking and lockout avoidance that updates the round robin priority token only when (1) the process request is granted and (2) there are no prior processes with |
| 5490261 |
Interlock for controlling processor ownership of pipelined data for a store in cache |
February 6, 1996 |
| Insures data integrity in process ownership indications by providing an ownership interlock on the data units in a pipeline to a store-in type of cache. An ownership interlock prevents any processor ownership change to occur (i.e. exclusive or readonly ownership) for a cache data unit un |
