| Patent Number |
Title Of Patent |
Date Issued |
| 5689721 |
Detecting overflow conditions for negative quotients in nonrestoring two's complement division |
November 18, 1997 |
| A method of detecting anomalous overflow conditions is used, in an exemplary embodiment, in implementing in a 486-type microprocessor, nonrestoring two's complement division for negative quotients using 2n bit dividends and n bit divisors. Each interative division step, an adder/subt |
| 5428622 |
Testing architecture with independent scan paths |
June 27, 1995 |
| A scan test architecture includes first and second serial scan paths for transferring test data to and from an integrated circuit's logic. A first clock controls transfer of information on the first scan path and a second clock controls transfer of data on the second scan path. The first |
| 5420989 |
Coprocessor interface supporting I/O or memory mapped communications |
May 30, 1995 |
| A coprocessor 18 comprises a bus controller 24 which further comprises a primary bus controller 28 and a secondary bus controller 30 that drive a floating point processor core 26. The primary bus controller 28 comprises a memory mapped bus interface 32 for processing memory mapped format |
| 5144570 |
Normalization estimator |
September 1, 1992 |
| A normalization circuit (24) which comprises a signed digit subtracter (25) coupled to operand registers (14, 19). The signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27). The pseudovalue converter (27) generates a |
| 5040138 |
Circuit for simultaneous arithmetic calculation and normalization estimation |
August 13, 1991 |
| An arithemtic circuit (10) which comprises an adder/rounder circuit (20) and a normalization estimation circuit (24) coupled in parallel to operand register (14, 19). A signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27 |
| 5020013 |
Bidirectional variable bit shifter |
May 28, 1991 |
| A bidirectional variable bit shifter (10) is disclosed which comprises a latch/input driver (12) coupled to a word shift array (14) coupled to a nibble shift array (16) coupled to a bit shift array (18) coupled to a latch/output driver (20). The bidirectional variable bit shifter (10) |
