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Inventor: Magane; Mitsuo
Address: Tokyo, JP
No. of patents: 3
Patents:
| Patent Number |
Title Of Patent |
Date Issued |
| 7969183 |
Semiconductor device |
June 28, 2011 |
| The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the |
| 7863927 |
Semiconductor device |
January 4, 2011 |
| The present invention is directed to adjust a resistance value of an output buffer on the basis of a resistance value of an external resistor. A potential according to a resistance ratio between an external resistor and each of resistance adjusters is detected by a code generator. In the |
| 6094069 |
Semiconductor integrated circuit having controlled output resistance of an output buffer circuit |
July 25, 2000 |
| An object is to provide a semiconductor integrated circuit capable of controlling the output resistance value of an output buffer circuit always at a given value without deteriorating the data transmission quality. D latches (60-63, 65-68) in latch circuit portions (16, 17) in an output |
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