| Patent Number |
Title Of Patent |
Date Issued |
| 6507183 |
Method and a device for measuring an analog voltage in a non-volatile memory |
January 14, 2003 |
| Presented is an analog voltage value measuring device for measuring any of a set of voltage references that are generated inside a memory architecture. The selected voltage to be measured is connected to a facility line through a multiplexer. The memory architecture includes a set of |
| 6392936 |
Method and apparatus for generating from a single supply line voltages internal to a flash memor |
May 21, 2002 |
| Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to |
| 6307396 |
Low-consumption TTL-CMOS input buffer stage |
October 23, 2001 |
| A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a |
| 6266222 |
ESD protection network for circuit structures formed in a semiconductor |
July 24, 2001 |
| An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one |
| 6208705 |
Electronic counter for a non-volatile memory device integrated on a semiconductor |
March 27, 2001 |
| An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which |
| 6204722 |
Electronic circuit for generating a stable voltage signal for polarizing during a reading step U |
March 20, 2001 |
| An electronic circuit generates a stable voltage signal for the polarization during a reading step of a UPROM redundancy cell incorporating at least one memory element of EPROM or Flash type, having at least one terminal to be polarized, and MOS transistors which connect such memory |
| 6157579 |
Circuit for providing a reading phase after power-on-reset |
December 5, 2000 |
| A circuit for providing a first reading phase after a Power-On-Reset in a memory device. The circuit includes a comparator, a reference generator that generates a reference voltage signal that is supplied to one input of the comparator, and a voltage divider that generates an output sign |
| 6157225 |
Driving circuit with three output levels, one output level being a boosted level |
December 5, 2000 |
| A driving circuit supplied by a supply voltage and a reference voltage, generates an output signal and comprises a first circuit adapted to selectively couple the output signal to the reference voltage or to an internal voltage line internal to the driving circuit in response to a fi |
| 6075750 |
Method and circuit for generating an ATD signal to regulate the access to a non-volatile memory |
June 13, 2000 |
| A method and a circuit generate a pulse synchronization signal (ATD) for timing the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input |
| 6031761 |
Switching circuit having an output voltage varying between a reference voltage and a negative vo |
February 29, 2000 |
| Switching circuit that receives a supply voltage, a reference voltage, a line adapted to carry a negative voltage and a control signal, the switching circuit capable of providing at an output a voltage alternatively equal to the reference voltage or to the voltage of the line in resp |
| 5955873 |
Band-gap reference voltage generator |
September 21, 1999 |
| A band-gap reference voltage generator comprises an operational amplifier comprising a first input and a second input, the first input being coupled to a first feedback network and the second input being coupled to a second feedback network both coupled to an output of the operational am |
| 5929674 |
Power on reset circuit with auto turn off |
July 27, 1999 |
| The present invention relates to an electronic power on reset circuit of the type including a comparator having at least two inputs and one output for receiving a first reference signal from a generator block and a second signal proportional to a supply voltage from a divider block and f |
| 5886925 |
Read circuit and method for nonvolatile memory cells with an equalizing structure |
March 23, 1999 |
| The read circuit presents a current mirror circuit including a first and second load transistor interposed between the supply line and a respective first and second output node. The first output node is connected to a cell to be read, the second output node is connected to a generating s |
| 5859797 |
Biasing circuit for UPROM cells with low voltage supply |
January 12, 1999 |
| A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a referen |
| 5822259 |
UPROM cell for low voltage supply |
October 13, 1998 |
| The present invention is directed to a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type having a control terminal and a conduction terminal to be biased, a register with inverters connected to the memory element, and MOS transistors connecting the |
| 5805500 |
Circuit and method for generating a read reference signal for nonvolatile memory cells |
September 8, 1998 |
| The current flowing through a cell to be read, forming part of a nonvolatile memory array and presenting a characteristic with a predetermined slope, is amplified N times and compared with a reference current presenting a two portion characteristic: a first portion extending between |
| 5717698 |
Method and apparatus for testing a network with a programmable logic matrix |
February 10, 1998 |
| A circuit architecture for testing a programmable logic matrix, e.g., the PLA type, has a group of input latches and a corresponding group of output latches connected to the matrix, and test information paths structured with at least one data bus and one address bus. The input latch and |
| 5708601 |
Integrated circuitry for checking the utilization rate of redundancy memory elements in a semico |
January 13, 1998 |
| An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default |
| 5687135 |
Count unit for nonvolatile memories |
November 11, 1997 |
| A count unit for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter and a number of registers equal in number to the count functions involved. The registers store the preceding count value and, when their |
| 5659509 |
Method for programming redundancy registers in a row redundancy integrated circuitry for a semic |
August 19, 1997 |
| A method for programming non-volatile row redundancy memory registers. Each register is associated with a respective pair of redundancy row and each one programmable to store in two subsets of a set of memory cells a pair of addresses of a respective pair of adjacent defective rows. Each |
| 5650671 |
Charge pump circuit |
July 22, 1997 |
| A charge pump circuit including a number of pull-up stages connected in parallel with one another between a reference potential line and an output line. Each stage includes a capacitor having a first terminal connected to a charging and discharging node, and a second terminal connected t |
| 5600600 |
Method for programming and testing a nonvolatile memory |
February 4, 1997 |
| A method for testing an electrically programmable non-volatile memory including a cell matrix and an internal state machine which governs the succession and timing of the memory programming phases includes excluding the internal state machine, modifying at least one of the control signal |
| 5600594 |
Threshold voltage measuring device for memory cells |
February 4, 1997 |
| A circuit device for measuring the threshold voltage distribution among electrically programmable, non-volatile memory cells, which device comprises a differential amplifier having a first input connected to a first circuit leg including at least one memory cell and a second input co |
| 5594703 |
End-of-count detecting device for nonvolatile memories |
January 14, 1997 |
| An end-of-count detecting device for nonvolatile memories, comprising a decoder in the form of a wired OR structure of a number of transistors of the same type, the gate terminals of which are fed with a count signal generated by a counter element and having a predetermined end-of-count |
| 5563826 |
Memory array cell reading circuit with extra current branch |
October 8, 1996 |
| A read circuit comprises at least one array branch connected to at least one bit line, and a reference branch connected to a reference line. The array and reference branches each comprise a precharge circuit and load interposed between the supply and the bit line and reference line r |
| 5541884 |
Method and circuit for suppressing data loading noise in nonvolatile memories |
July 30, 1996 |
| In a nonvolatile memory comprising a data amplifying unit and an output element mutually connected by a connection line, the noise suppressing circuit comprises a network for generating a noise suppressing signal which is synchronized substantially perfectly with a signal controlling |
| 5532972 |
Method and circuit for timing the reading of nonvolatile memories |
July 2, 1996 |
| A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noi |
| 5519656 |
Voltage regulator for programming non-volatile and electrically programmable memory cells |
May 21, 1996 |
| A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage being powered between a first and a second voltage reference and having a first input terminal connected to a resistive divider of the first reference voltage and an output terminal fed |
| 5515332 |
Method and circuit for timing the loading of nonvolatile-memory output data |
May 7, 1996 |
| A load timing circuit including an output simulation circuit similar to the output circuits of the memory, so as to present the same propagation delay; a simulating signal source for generating a data simulating signal; a synchronizing network for detecting a predetermined switching edge |
| 5499217 |
Bias circuit for a memory line decoder driver of nonvolatile memories |
March 12, 1996 |
| A memory line decoding driver is so biased that the P channel pull-up transistor biasing the final inverter conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one |
| 5493531 |
Integrated circuitry for checking the utilization rate of redundancy memory elements in a semico |
February 20, 1996 |
| An integrated circuit for checking the utilization rate of redundancy memory elements in semiconductor memory device, comprising a matrix of memory elements and a redundancy circuitry which comprises a plurality of programmable non-volatile memory registers, each supplied with address |
